I have been trying to model a dll in simulink but to no results.
My problem is modeling the voltage controlled delay line. I tried to use variable transport delay. But it didn't work well.
Can anybody give me an example of modeling DLL or some materials related to that?
The Simulink block "Variable Transport Delay" is found in 6.5 and 7.0 at least and could model a DLL.
The problem could be that the "Variable Transport Delay" uses a discrete time circular buffer. That is to allow logic, real and complex values to path at the input at a higher rate than the delay time. That limit time resolution to discrete time steps and is overkill for the application.
You should use an integrator where the integration constant is multiplied with the input signal and the integrator integrate up to a threshold and then trigger a simple register and reset. The integration start with the incoming of a new edge. The register path this signal to output if the integrator reach the level.
I too need the simulink modelling and simulation of digital delay locked loop (DLLs). Can anyone post or upload some design concepts and examples using simulink.