Need full verilog code for 16-bit adder with carry save

[rsharitwal]

verilog carry

please send me full verilog code for 16-bit adder with carry save.please send it as fast as you can.I need it very urgently.

 

[maizic]

verilog assign [3:0]

In fact, I have the code write 5,6 years ago by myself, I don't advocate one to get code from this way, if you understand the method of carry save, it's very simple. but I still offer to you this time

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Code Verilog - [expand]
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module RCA4(A,B,Ci,So,Co);
input [3:0] A,B;
input Ci;
output [3:0] So;
output Co;
wire c1,c2,c3,c4;
wire g0,g1,g2,g3;
wire p0,p1,p2,p3;
 
 assign g0=A[0]&B[0];
 assign g1=A[1]&B[1];
 assign g2=A[2]&B[2];
 assign g3=A[3]&B[3];
 
 assign p0=A[0]|B[0];
 assign p1=A[1]|B[1];
 assign p2=A[2]|B[2];
 assign p3=A[3]|B[3];
 
 assign c1=g0|(p0&Ci);
 assign c2=g1|(p1&g0)|(p1&p0&Ci);
 assign c3=g2|(p2&g1)|(p2&p1&g0)|(p2&p1&p0&Ci);
 assign c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&Ci);
 assign Co=c4;
       
 assign So[0]=g0^p0^Ci;
 assign So[1]=g1^p1^c1;
 assign So[2]=g2^p2^c2;
 assign So[3]=g3^p3^c3;
endmodule
 
 
module CSA8(A,B,Ci,So,Co);
input [7:0] A,B;
input Ci;
output [7:0] So;
output Co;
 
wire [3:0] stemp1,stemp0;
wire c4;
wire c80,c81;
 
RCA4 RCA4in(A[3:0],B[3:0],Ci,So[3:0],c4);
RCA4 RCA41 (A[7:4],B[7:4],1'b1,stemp1,c81);
RCA4 RCA40 (A[7:4],B[7:4],1'b0,stemp0,c80);
 
assign So[7:4] = c4?stemp1:stemp0;
assign Co=       c4?c81:c80;
 
endmodule
 
module CSA16(A,B,Ci,So,Co);
input [15:0] A,B;
input Ci;
output [15:0] So;
output Co;
 
wire [7:0] stemp1,stemp0;
wire c8;
wire c160,c161;
 
CSA8 CSA8in(A[7:0],B[7:0],Ci,So[7:0],c8 );
CSA8 CSA81 (A[15:8],B[15:8],1'b1,stemp1,c161);
CSA8 CSA80 (A[15:8],B[15:8],1'b0,stemp0,c160);
 
assign So[15:8] = c8?stemp1:stemp0;
assign Co=        c8?c161:c160;
 
endmodule

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[rsharitwal]

Re: verilog code very urgent

thank you very much sir.actually I understood the logic behind it.I am doing a project that uses it. because i have very less time to submit it.i made my own code but I am getting a probelm with it.that's i was asking for helping.thank you again.

 

[Naveed4u]

Re: verilog assign [3:0]

Hi I need some description about this code
Can u narrate this code Please

I have this assignment of full adder and to submit very shortly hardly in three days

I cannot be able to write the correct code for it
I have found ur code and i think if u give some description it would be easy to understand some key features

Thank you
And take care

In fact, I have the code write 5,6 years ago by myself, I don't advocate one to get code from this way, if you understand the method of carry save, it's very simple. but I still offer to you this time

module RCA4(A,B,Ci,So,Co);
input [3:0] A,B;
input Ci;
output [3:0] So;
output Co;
wire c1,c2,c3,c4;
wire g0,g1,g2,g3;
wire p0,p1,p2,p3;

assign g0=A[0]&B[0];
assign g1=A[1]&B[1];
assign g2=A[2]&B[2];
assign g3=A[3]&B[3];

assign p0=A[0]|B[0];
assign p1=A[1]|B[1];
assign p2=A[2]|B[2];
assign p3=A[3]|B[3];

assign c1=g0|(p0&Ci);
assign c2=g1|(p1&g0)|(p1&p0&Ci);
assign c3=g2|(p2&g1)|(p2&p1&g0)|(p2&p1&p0&Ci);
assign c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&Ci);
assign Co=c4;

assign So[0]=g0^p0^Ci;
assign So[1]=g1^p1^c1;
assign So[2]=g2^p2^c2;
assign So[3]=g3^p3^c3;
endmodule


module CSA8(A,B,Ci,So,Co);
input [7:0] A,B;
input Ci;
output [7:0] So;
output Co;

wire [3:0] stemp1,stemp0;
wire c4;
wire c80,c81;

RCA4 RCA4in(A[3:0],B[3:0],Ci,So[3:0],c4);
RCA4 RCA41 (A[7:4],B[7:4],1'b1,stemp1,c81);
RCA4 RCA40 (A[7:4],B[7:4],1'b0,stemp0,c80);

assign So[7:4] = c4?stemp1:stemp0;
assign Co= c4?c81:c80;

endmodule

module CSA16(A,B,Ci,So,Co);
input [15:0] A,B;
input Ci;
output [15:0] So;
output Co;

wire [7:0] stemp1,stemp0;
wire c8;
wire c160,c161;

CSA8 CSA8in(A[7:0],B[7:0],Ci,So[7:0],c8 );
CSA8 CSA81 (A[15:8],B[15:8],1'b1,stemp1,c161);
CSA8 CSA80 (A[15:8],B[15:8],1'b0,stemp0,c160);

assign So[15:8] = c8?stemp1:stemp0;
assign Co= c8?c161:c160;

endmodule

 

[lostinxlation]

You can find CSA in any textbook. Read them.

 

[ZAKIR HUSSAIN]

Re: verilog carry

please send me full verilog code for 16-bit adder with carry save.please send it as fast as you can.I need it very urgently.

this is the code for the .. 16 bit carry propagate adder circuit.

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Code Verilog - [expand]
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module cla(sum,c0,a,b,ci);
input [7:0]a,b;
input ci;
output[7:0]sum;
output c0;
wire p0,p1,p2,p3,p4,p5,p6,p7,g0,g1,g2,g3,g4,g5,g6,g7;
wire c1,c2,c3,c4,c5,c6,c7,c8;
assign 
p0=a[0]^b[0],
p1=a[1]^b[1],
p2=a[2]^b[2],
p3=a[3]^b[3],
p4=a[4]^b[4],
p5=a[5]^b[5],
p6=a[6]^b[6],
p7=a[7]^b[7],
g0=a[0]&b[0],
g1=a[1]&b[1],
g2=a[2]&b[2],
g3=a[3]&b[3],
g4=a[4]&b[4],
g5=a[5]&b[5],
g6=a[6]&b[6],
g7=a[7]&b[7];
assign
c1=g0|(p0&ci),
c2=g1|(p1&g0)|(p1&p0&ci),
c3=g2|(p2&g1)|(p2&p1&g0)|(p2&p1&p0&ci),
c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&ci),
c5=g4|(p4&g3)|(p4&p3&g2)|(p4&p3&p2&g1)|(p4&p3&p2&p1&g0)|(p4&p3&p2&p1&p0&ci),
c6=g5|(p5&g4)|(p5&p4&g3)|(p5&p4&p3&g2)|(p5&p4&p3&p2&g1)|(p5&p4&p3&p2&p1&g0)|(p5&p4&p3&p2&p1&p0&ci) ,
c7=g6|(p6&g5)|(p6&p5&g4)|(p6&p5&p4&g3)|(p6&p5&p4&p3&g2)|(p6&p5&p4&p3&p2&g1)|(p6&p5&p4&p3&p2&p1&g0)|( p6&p5&p4&p3&p2&p1&p0&ci),
c8=g7|(p7&g6)|(p7&p6&g5)|(p7&p6&p5&g4)|(p7&p6&p5&p4&g3)|(p7&p6&p5&p4&p3&g2)|(p7&p6&p5&p4&p3&p2&g1)|( p7&p6&p5&p4&p3&p2&p1&g0)|(p7&p6&p5&p4&p3&p2&p1&p0& ci);
assign
sum[0]=p0^ci,
sum[1]=p1^c1,
sum[2]=p2^c2,
sum[3]=p3^c3,
sum[4]=p4^c4,
sum[5]=p5^c5,
sum[6]=p6^c6,
sum[7]=p7^c7,
c0=c8;
endmodule
 
 
// FOR THE TEST BENCH
 
module testbench();
  
  wire [7:0]sum;
  wire c0;
  reg ci;
  reg [7:0]a,b;
  cla g1 (sum,c0,a,b,ci);
  initial
  begin
  ci = 1'b0;
  a = 8'b10101011;
  b = 8'b11010101;
end
endmodule

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