Finite state machine can be designed for processes/ modules that may be running continuously to generate certain output signals , based on clock .
Each state in a FSM is traversed through a condition ,
FSM stays in the same state and generate signals of that sate continously until the condition is met .
A crunch about FSM is all what i have given you .
More can be found in some good design Books such as
FSM:Finite state machine is a behavior model of programming in digital design where data is transformed from one state to another.
Briefly...
VHDL is an intergrated circuit language through which you can define the behavior/structure of a given circuit.
VHDL is compatible to many FPGA's where in you have to download the code and check the application.