need explanation for the below DFT tasks performed?

Hi all,
can anyone please explain me how to perform below DFT tasks..


1. Memory BIST generation/insertion and verification
2. Scan insertion
3. Test Logic insertion (PLL wrapper, scan router, clock chopper) and verification
4. IP insertion and verification
5. JTAG insertion and verification
6. ATPG generation, verification
7. DRC violation analysis and coverage improvements
8. Formal Verification

1-bist could be done by a hardware block or by software, in hardware case, different tools insert this during the synthesis, or directly RTL code
2-done by synthesis tool in general
3-synthesis tool could do some test point insertion, or DFT tool (like Tessent-DFT compiler) do it on RTL or during the synthesis
4- what do you mean by ip insertions?, normaly you test it before backend, no?
5-same as test point, the JTAG could be add automaticly at RTL or netlist level by DFT tool.
6-ATPG generation is done after scan insertion by atpg tool like fastscan-tetramax
7-DRC is very large, all tools have their own DRC reports. At ATPG level, you need to analyze the different type of DRC and fix them if necessary. for the coverage improvement, some tool in Tessent suite (for example) provide some guide to increase the coverage, after you need to analyze the weak block and find the reason.
8-done along the back flow, to first check (lint) the RTL code and after that check RTL versus different netlist at all major steps.