<Need Clarification>Use of Dummy poly in different technologies

[cmoslayoutguide]

Is there any functional difference in the dummy poly we use in deep sub micron technologies and micron technologies.

I learned that , dummy poly is used to protect the gate while etching....

Is it the same etching mechanism that we are following even for the lower nodes?

 

[Colbhaidh]

They are the same. They are not really protecting the gate but making the finished dimension of the gate more controllable.
If a long narrow poly line sitting on its own, is the same as 10 lines exactly the same but very closely spaced, then the narrow lines etch faster (less poly to be removed local to the lines) compared to the single line isolated from all others. This means the dense lines will see more "over etch" than the isolated line and may be slightly narrower. This could have a major impact on matching.
Adding dummy poly lines to make sure no line is really left isolated guarantees all lines end up the same size.
Note that depending on the plasma process this effect could be the reverse - isolated lines end up narrower than dense lines because there is less resist around a narrow isolated line, and resist is used not only to block the etch, but as it is attacked, it forms polymer on the poly sidewalls, which stops them being undercut (made smaller).

 

[VLSI_Learner]

Can you be more specific. I mean I didn't get your answer. Can you please explain it more easily?

 

[Colbhaidh]

There are two primary effects. The first is the Lithography (imaging the poly lines in the resist).
If you project a single isolated poly line from the mask onto the resist on the wafer, it will have a width of say 0.9um.
Now if you project a nested (dense) set of poly lines (exactly the same width s as the isolated line, closely spaced together and look at the middle poly line, it will have a dimension of (say) 0.87um, This is due to diffraction.
So before we even start etch, there is a difference between a single poly line and dense poly lines close together. The single isolated line will always be wider. To avoid mis-match, you must avoid using isolated poly lines for critical gates. So this is the first reason for using two dummy poly lines either side of the gate. The gate is never isolated.
But the problem does not end there. Once the resist is patterned, the poly is then etched in a Reactive Ion Etch (RIE) system. Now you must think is 3 dimensions.
The RIE system works by creating a plasma which create active flourine reactants that will attack and etch away polysilicon. The plasma also create a polymer which deposits everywhere including the wafer surface. The polymer blocks etching. So the RIE bombards the wafer surface with ions which hit the wafer surface like an implant. This removes polymer from the surface allowing the fluorine radicals to attack and remove polysilicon. But as the poly is etch downward either side of the resist pattern, polymer deposits on the exposed vertical edges of polysilicon stopping any sideways etch underneath the resist pattern.
Now when all the poly is etched vertically (except beneath any resist pattern, the gate oxide is exposed beneath the poly. To make sure all the poly is removed over the entire wafer surface the etch continues after the gate oxide is exposed. The etch of the oxide releases oxygen locally to the polymer protecting the remaining poly beneath the resist pattern. However the oxygen will attack the polymer and remove it allowing the fluorine radicals to start etching sideways beneath the resist pattern.
This effect is competing the constant deposition of polymer. The net result is that after etch, the width of the poly will be slightly smaller than the resist image.
Now depending on how the RIE is set up, dense poly lines (where there is less poly locally to etch away, may clear faster than isolated. So the gate oxide is exposed sooner and the sidewall polymer is attacked for longer. Therefore dense lines may have even smaller widths than isolated. Or the RIE could be set up to do the opposite.
Anyway, the point is, isolated lines will be sized slightly differently the dense, so dummy poly is used to reduce this effect.

 

[VLSI_Learner]

Thank you. It's very nice explanation. Though the fabrication part (the etching mechanism) is still confusing, I want one more clarification.

Let me know if I am wrong:
The purpose of etching is to remove the unwanted Sio2, photo mask and other unwanted layers. But some desired layers are also get etched at their edges (for our discussion the desired layer is poly layer). If we use a dense poly the desired poly get etched more, instead if we use nested poly lines the desired poly etch is less. But my question is I have only one transistor, which has only one poly gate. Say the poly width is 30nm. The single transistor poly width is not going to increase or decrease. So it's still not clear how the dummy poly will help here?

 

[Colbhaidh]

The need for dummy lines is where transistor need to be exactly matched. If the particular process gives an isolated poly width of 30nm where the transistor was drawn on the mask at 30nm but gives a dense line of 27nm when it was drawn on the mask at 30nm, then these two transistors (designed to be identical) are not. So what if you need them to be identical? You cannot make a dense transistor isolated so you make the isolated transistor dense by adding dummy lines. Then both isolated and dense transistors (drawn at 30nm) are 27nm and matched.
Now since there are more dense than isolated transistors, the Foundry will often set up the process such that drawn (designed) transistors of 30nm turn out to be 30nm when dense and say 33nm for isolated. That way most of the transistors behave as designed.