Need Clarification on Ft & Fmax devices.

[suria3]

ft fmax equation

Dear People,

I need some clarification on the terms of fT (frequency transition) & fmax (maximum frequency). As we know that ft means the value when current gain of the device (BJT/CMOS) is unity whereby fmax means the value when power gain is unity. So, when i do SiGE design, from the design manual i could see that fmax is about 47Ghz. Is this referring to the max frequency that a single BJT can operate without any load to input or at the output? What are the other things that i can understand when they say having a ft & fmax of this value? Hope i can get some clear explanation from this forum.

Thanks in advance,
Suria3

 

[flatulent]

compare cmos fmax to bipolar fmax

The Ft is a projection of beta vs frequency for a short circuit load. Real circuits with sources with a thevenin equivalent impedance and finite load impedance have much less gain bandwith product at the higher frequencies. You can recover some of this reduction by putting a resistor from the emitter to ground.

Fmax is also another idealized maximum limit under the best of source and load conditions.

 

[radiohead]

fmax circuit equation

The real bandwidth of an amplifier depends on source and load impedance, parasitic capacitances included. So it is impossible to obtain the ft bandwidth. You better look at it as a figure of merit, to compare different processes.

 

[suria3]

figures of merit ft fmax

The Ft is a projection of beta vs frequency for a short circuit load. Real circuits with sources with a thevenin equivalent impedance and finite load impedance have much less gain bandwith product at the higher frequencies. You can recover some of this reduction by putting a resistor from the emitter to ground.

Fmax is also another idealized maximum limit under the best of source and load conditions.

Flatulent,

As u said, the response of beta vs frequency for a short circuit load, is this means the single BJT is simulated such a way that without any load (ac grounded) and given a AC input signal. So, the ft is the frequency where not any capacitances is included (parasitics, load and etc) .

Thanks,
Suria3

 

[krashkealoha]

device ft fmax

A useful equation which relates ft to fmax (bipolar technology) is:

Fmax = (Ft/(8*pi*rbb*Cbc))^0.5 [1]

Fmax is much more useful than Ft in a high-speed large-signal application. If the technologist optimized rbb & Cbc with Ft, then typically Fmax > Ft. In another words, if Foundry A Ft = Foundry B Ft, but Foundry A Fmax > Foundry B Fmax => Foundry A circuit will be faster than Foundry B.

Using equation [1] as a guideline, these are some conditions that would lead to degradation of Fmax with respect to Ft (Fmax < Ft):

1) Ft is high, rbb is high: Peak base concentration is not high enough, therefore increasing base resistance. The increase in base resistance degrades Fmax. Other symptoms would include low Early voltage, low BVceo and high Beta.

2) Ft is high, rbb is high, Cbc is high => Fmax is degraded. An unoptimized selective implanted collector (SIC) implant, which is used to suppress Kirk effect, is positioned to close to the bottom of the base profile. This causes to effective base width to decrease which increases base resistance. In addition, since the SIC implant is ~1e17/cm3 vs. ~2e16/cm3 concentration for n-epi/nwell, your collector-base capacitance will increase.

From a circuit designer's perspective, Cbe ~ gm/(2*pi*Ft). Therefore, your diffusion capacitance is dominated by the Ft of your transistor. On the other hand, a high Cbc and rbb will limit the bandwidth of your circuit. In addition, a high rbb will increase your input noise thus degrading your circuit's input sensitivity.

 

[krashkealoha]

fequency ft devices

Suria,

In response to your question to Flatulent.

In your Ft simulation, there are no external elements included in the simulation, with the exception of 50 ohm ports on the input and output to simulate the s-parameters (simulator dependent).

In actual measurements, there are series resistances and load capacitances from the test structure and measurement equipment, but these values are de-embedded from the final results.

The parasitics of the transistor do impact your Ft vs. Ic (bipolar case) curve. Cje & Cjc will degrade your Ft in the low current regime (below peak Ft). This will impact such circuits as a LNA which does not operate at peak Ft. On the other hand, Rc is one of the contributors on how fast your Ft value will roll-off after peak Ft. As Ic increases large Rc will cause your transistor to go into quasi-sat and it will kill your Ft. Circuits such as large-signal high-freq drivers/receivers are affected by this.

 

[yolande_yj]

f max ft

What is the relation between linearity of a BJT and its Ft or Fmax?

When designing LNA or Mixer, how Ft and Fmax help to determin the device size and supply current?

Thanks.