Need advice on area/power of ADC designed in CMOS technology

low area ADC

I am looking for an advice on area/power of ADCs designed in CMOS technology.

What is the best architecture SAR, pipline, Segma delta, etc for a low area ADC given that we are sampling in the Khz range. Just low area design.

Any thoughts?

Technology can be 90nm 180nm .35um or .5um

resolution is 8-bits or 10-bits

Thanks

Re: low area ADC

For kHz, just use a SAR topology. It is suitable for 8-12bit resolution.

Bastos

Re: low area ADC

Algorithmic ADC

Re: low area ADC

There are many factors to be considered when choosing a data
converte.When selecting an Analog-to-Digital Converter (ADC) for a particular
application, a good first criteria is to look at the topology of the ADC.

SAR---->Simple operation, lowcost, low power.
Delta-Sigma---->Slow, moderate cost.
Flash---->Fast, expensive, large power requirements.
Pipeline---->Fast, expensive, large power requirements.

The most popular and versatile converter is the Successive
Approximation Register (SAR) type.
you must use serial type ADC to save area.in this condition i suggest you to use AD7766 (see data sheet for more information) .Serial devices tend to be slower, dissipate less power (modern converters tend to have auto powerdown between samples) and take up less PWB (Printed wiring board) area

for more information see the following link:

https://focus.ti.com/lit/ml/slap082/slap082.pdf