Need a explanation on This Phase shifted Full bridge Zero Voltage switching waveform

[Pulasthi_Perera]

I have design and tested a Prototype of a phase shifted full bridge with 400V/72V with 2.5kW.When i run the converter at 1kW power about 15A output with 72V,attached wavefrom can be observed at the primary of the transformer.

I have designed the transformer and adjusted the deadtime allowing the converter to have zero voltage switching.

When current is increased the EMI noise is also increased.
I need your help to get a sense of this waveform and why this occurs
Thank you in advance!!

YELLOW line is the primary voltage and BLUE is the inverted Secondary Voltage

 

[Easy peasy]

far too little information supplied - to make any useful comment.

--- Updated Aug 27, 2024 ---

increased EMI will be from your output diodes - show the Vak waveforms !

 

[Pulasthi_Perera]

far too little information supplied - to make any useful comment.

Can i know what are the information you need to give a explaination

 

[Easy peasy]

Schematic, Vds waveforms, Vgs waveforms, Vak waveforms of o/p diodes - and what type they are

 

[Pulasthi_Perera]

Schematic, Vds waveforms, Vgs waveforms, Vak waveforms of o/p diodes - and what type they are

No ouput diodes they are replaced by a SR

 

[Magnethicc]

Can you show the Vgs of the MOSFETs in primary (and in the sec. If using rectifier MOSFETs)

I suspect not enough energy in the leakage inductace in the primary during the dead-time so it resonates.

As for the EMI you should look for the current loops with high di/dt.


Would like to hear what others think.

 

[D.A.(Tony)Stewart]

I see a transition 0 V to output V with 13 MHz resonance with a few decaying cycles during Tr= 130 ns

Parasitic ESL for Vgs = ? Ciss=? Coss? RdsOn =? Lpri = ? DT = 130ns? XFMR SRF= 13 MHz?

Cdg/Cgs ratio causing self-turn-on during off.

k=0.995

 

[Easy peasy]

No ouput diodes they are replaced by a SR

Doesn't matter - the SR is off - just before the internal diode takes over the current and then has to reverse recover - causing your EMI . ..

we still can't see the gate drive along with the Vds

 

[Easy peasy]

Ah yes - after a close look - there is also the issue mentioned above of not enough stored energy at the load and Vin you are using to swing the volts right up at turn off

This is a thing for the phase shift converter - below a certain load there is no full transition and hence loss of proper soft switching - the shim inductor and diodes lower the level at which proper ZVS is lost - but you still get it below a certain load.

 

[Pulasthi_Perera]

This is a thing for the phase shift converter - below a certain load there is no full transition and hence loss of proper soft switching - the shim inductor and diodes lower the level at which proper ZVS is lost - but you still get it below a certain load.

Yes i understand what is the reason for the voltage bump that appears before the FET is actually turns on?

 

[cupoftea]

Yes from top scope shot is seen a resonant period of some 200ns after the primary is switched in.
Do you use a series blocking capacitor?...if so, what is resonant period of it with the primary leakage inductance?

Have you produced the "representatve simulation" yet in LTspice?...if not, i will send you a PSFB in LTspice eand you can adapt it to your spec?.....the sim is good at doing simple stuff liek LC resonances.
..in fact, ive attached the whole PSFB folder...there are sims in there of PSFB if you want to dig one out?
But my bet, looking at the smoothly sinusoidal resonance, is that its the series cap and the leakage L ringing with each other.

Absolutely expected...big voltage step input to a high Q series LC resoannt cct...will ring like mad....we cannot stop it...its mother nature.

 

[Pulasthi_Perera]

Do you use a series blocking capacitor?

no i do not use a blocking capacitor

i will send you a PSFB in LTspice eand you can adapt it to your spec?

if you can i will be much obliged. I done a simulation in Matlab to verify the control loop but not in LTspice

Absolutely expected...big voltage step input to a high Q series LC resoannt cct...will ring like mad....we cannot stop it...its mother nature.

the thing i can't understand is whether this voltage waveform is normal or do i need to do something about it. I want to clearly understand why that voltage bump appears in the primary.

My guess is ,this is the voltage seen at the primary due to resonation of transformer leakage inductance and Mosfet's Coss capacitors in the deadtime

Am i Achieving the zero voltage switching or do i need to adjust the dead time or maybe increase the leakage or add a shim inductor

 

[Easy peasy]

the volts try to rise - but there is insufficient energy stored - so it goes down again until the gate drive is applied forcing the voltage high.

 

[Pulasthi_Perera]

the volts try to rise - but there is insufficient energy stored - so it goes down again until the gate drive is applied forcing the voltage high.

are you suggesting that the MOSFET is tries to turn on?

 

[Easy peasy]

I'm not suggesting - I have said.

--- Updated Aug 28, 2024 ---

this is why showing the gate drive at the same time as the mid point is so instructive.

 

[cupoftea]

woops sorry, here it is now on PSFB
Ok..its too big...so here it is linked..

Phase Shift Full Bridge converter.zip

drive.google.com

 

[mtwieg]

From what I understand, that waveform is at medium-load, so one would expect the stored energy to be sufficient to soft switch the bridge completely.

But you say yellow is primary voltage, which I assume is not the same as the bridge output voltage (on the other side of your series inductance). What does the bridge output voltage look like?

 

[Easy peasy]

From what I understand, that waveform is at medium-load, so one would expect the stored energy to be sufficient to soft switch the bridge completely.

We don't know if there is any shim inductor, or, how high the pri side leakage is on the Tx - you can see in the waveform ( just - LHS ) that the transition at the end of the power pulse ( some times called the leading leg transition ) IS ZVS, but after the circulating current period there is insufficient energy for ZVS on the passive to active transition ( sometimes called the lagging leg transition ) - this can easily happen at mid load for a given design - and appears to be happening here.

 

[mtwieg]

We don't know if there is any shim inductor, or, how high the pri side leakage is on the Tx - you can see in the waveform ( just - LHS ) that the transition at the end of the power pulse ( some times called the leading leg transition ) IS ZVS

You might be right, but impossible to really tell without seeing Vgs waveforms. Need much more info from OP in general.

 

[cupoftea]

OP may like to show us a scope shot of both Vgs and Vds of a FET. We will then see if the Vds has gone to zero just before the FET is switched ON.
(sorry just noticed Easy Peasy already requested this some time back)
That would totally clinch it for us.