[SOLVED] Need a comparator which is synthesizable and without if-else statements

hi,

Haddr i s my input and EN_ADDR/ST_ADDR are my parameters.


always @(Haddr)
begin
case(Haddr)
(Haddr <= EN_ADDR_0 && Haddr >= ST_ADDR_0) :begin
hsel=32'b0000_0000_0000_0000_0000_0000_0000_0001;
Hslavenum=5'b00000;
end
(Haddr <= EN_ADDR_1 && Haddr >= ST_ADDR_1) :begin
hsel=32'b0000_0000_0000_0000_0000_0000_0000_0010;
Hslavenum=5'b00001;
end
(Haddr <= EN_ADDR_2 && Haddr >= ST_ADDR_2) :begin
hsel=32'b0000_0000_0000_0000_0000_0000_0000_0100;
Hslavenum=5'b00010;
end
(Haddr <= EN_ADDR_3 && Haddr >= ST_ADDR_3) :begin
Hslavenum=5'b00011;
hsel=32'b0000_0000_0000_0000_0000_0000_0000_1000;
end
(Haddr <= EN_ADDR_4 && Haddr >= ST_ADDR_4) :begin
Hslavenum=5'b00100;
hsel=32'b0000_0000_0000_0000_0000_0000_0001_0000;
end
(Haddr <= EN_ADDR_5 && Haddr >= ST_ADDR_5) :begin
Hslavenum=5'b00101;
hsel=32'b0000_0000_0000_0000_0000_0000_0010_0000;
end
(Haddr <= EN_ADDR_6 && Haddr >= ST_ADDR_6) :begin
Hslavenum=5'b00110;
hsel=32'b0000_0000_0000_0000_0000_0000_0100_0000;
end
(Haddr <= EN_ADDR_7 && Haddr >= ST_ADDR_7) :begin
Hslavenum=5'b00111;
hsel=32'b0000_0000_0000_0000_0000_0000_1000_0000;
end
(Haddr <= EN_ADDR_8 && Haddr >= ST_ADDR_8) :begin
hsel=32'b0000_0000_0000_0000_0000_0001_0000_0000;
Hslavenum=5'b01000;
end
(Haddr <= EN_ADDR_9 && Haddr >= ST_ADDR_9) :begin
Hslavenum=5'b01001;
hsel=32'b0000_0000_0000_0000_0000_0010_0000_0000;
end
(Haddr <= EN_ADDR_10 && Haddr >= ST_ADDR_10):begin
Hslavenum=5'b01010;
hsel=32'b0000_0000_0000_0000_0000_0100_0000_0000;end
(Haddr <= EN_ADDR_11 && Haddr >= ST_ADDR_11):begin
Hslavenum=5'b01011;
hsel=32'b0000_0000_0000_0000_0000_1000_0000_0000;end
(Haddr <= EN_ADDR_12 && Haddr >= ST_ADDR_12):begin
hsel=32'b0000_0000_0000_0000_0001_0000_0000_0000;
Hslavenum=5'b01100;end
(Haddr <= EN_ADDR_13 && Haddr >= ST_ADDR_13):begin
hsel=32'b0000_0000_0000_0000_0010_0000_0000_0000;
Hslavenum=5'b01101;end
(Haddr <= EN_ADDR_14 && Haddr >= ST_ADDR_14):begin
hsel=32'b0000_0000_0000_0000_0100_0000_0000_0000;
Hslavenum=5'b01110;end
(Haddr <= EN_ADDR_15 && Haddr >= ST_ADDR_15):begin
hsel=32'b0000_0000_0000_0000_1000_0000_0000_0000;
Hslavenum=5'b01111;end
(Haddr <= EN_ADDR_16 && Haddr >= ST_ADDR_16):begin
hsel=32'b0000_0000_0000_0001_0000_0000_0000_0000;
Hslavenum=5'b10000;end
(Haddr <= EN_ADDR_17 && Haddr >= ST_ADDR_17):begin
hsel=32'b0000_0000_0000_0010_0000_0000_0000_0000;
Hslavenum=5'b10001;end
(Haddr <= EN_ADDR_18 && Haddr >= ST_ADDR_18):begin
hsel=32'b0000_0000_0000_0100_0000_0000_0000_0000;
Hslavenum=5'b10010;end
(Haddr <= EN_ADDR_19 && Haddr >= ST_ADDR_19):begin
hsel=32'b0000_0000_0000_1000_0000_0000_0000_0000;
Hslavenum=5'b10011;end
(Haddr <= EN_ADDR_20 && Haddr >= ST_ADDR_20):begin
hsel=32'b0000_0000_0001_0000_0000_0000_0000_0000;
Hslavenum=5'b10100;end
(Haddr <= EN_ADDR_21 && Haddr >= ST_ADDR_21):begin
hsel=32'b0000_0000_0010_0000_0000_0000_0000_0000;
Hslavenum=5'b10101;end
(Haddr <= EN_ADDR_22 && Haddr >= ST_ADDR_22):begin
hsel=32'b0000_0000_0100_0000_0000_0000_0000_0000;
Hslavenum=5'b10110;end
(Haddr <= EN_ADDR_23 && Haddr >= ST_ADDR_23):begin
hsel=32'b0000_0000_1000_0000_0000_0000_0000_0000;
Hslavenum=5'b10111;end
(Haddr <= EN_ADDR_24 && Haddr >= ST_ADDR_24):begin
hsel=32'b0000_0001_0000_0000_0000_0000_0000_0000;
Hslavenum=5'b11000;end
(Haddr <= EN_ADDR_25 && Haddr >= ST_ADDR_25):begin
hsel=32'b0000_0010_0000_0000_0000_0000_0000_0000;
Hslavenum=5'b11001;end
(Haddr <= EN_ADDR_26 && Haddr >= ST_ADDR_26):begin
hsel=32'b0000_0100_0000_0000_0000_0000_0000_0000;
Hslavenum=5'b11010;end
(Haddr <= EN_ADDR_27 && Haddr >= ST_ADDR_27):begin
hsel=32'b0000_1000_0000_0000_0000_0000_0000_0000;
Hslavenum=5'b11011;end
(Haddr <= EN_ADDR_28 && Haddr >= ST_ADDR_28):begin
hsel=32'b0001_0000_0000_0000_0000_0000_0000_0000;
Hslavenum=5'b11100;end
(Haddr <= EN_ADDR_29 && Haddr >= ST_ADDR_29):begin
hsel=32'b0010_0000_0000_0000_0000_0000_0000_0000;
Hslavenum=5'b11101;end
(Haddr <= EN_ADDR_30 && Haddr >= ST_ADDR_30):begin
hsel=32'b0100_0000_0000_0000_0000_0000_0000_0000;
Hslavenum=5'b11110;end
(Haddr <= EN_ADDR_31 && Haddr >= ST_ADDR_31):begin
hsel=32'b1000_0000_0000_0000_0000_0000_0000_0000;
Hslavenum=5'b11111;end
default: begin
default_slave=1'b1;
dec_error=1'b1;
end
endcase
end


suggest me if it is synthesizable, if not i want mutually exclusive comparator without if else statements how can i do that.

Instead of posting 400 lines of unreadable code, why don't you just TRY SYNTHESING IT???

Using only a code fragment....


You can't do this the (Haddr <= EN_ADDR_0 && Haddr >= ST_ADDR_0) can't be some comparison operation. it has to be a one of the possible values of Haddr.

Have you even read anything about how to write a Verilog case statement? I think you should read this...
https://www.asic-world.com/verilog/vbehave2.html

If you want a comparison you'll have to use an if-else construct.

The comparisons better be mutually exclusive....and you better cover all possible "a" values otherwise you'll end up with a latch.

Note: I haven't tested this code, but I think it should work. You should try a simple testcase with a[3:0] and compare say 4 groups of a where a is 0-1, 2-3, 4-5, and 6-7 then synthesize that and see what the implementation looks like.

-alan