nearly accurate counter with VHDL

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mohammadmother

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hi every body
i write a vhdl code that is nearly accurate counter
every 1.34 s the LED will be ++
(2^27*10ns = 1.34 s )
please tell me what is it's problem because in ISIM i don't got the
answer
_________________________________________
Code VHDL - [expand]
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------------------------------------------------------------------------ 
----------
-- Company:
-- Engineer:
--
-- Create Date:    08:48:18 09/28/2014
-- Design Name:
-- Module Name:    count - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
------------------------------------------------------------------------ 
----------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.STD_logic_unsigned.ALL;
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity count is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           sw1 : in  STD_LOGIC;
           LED : out std_logic_vector(7 downto 0));
end count;
architecture Behavioral of count is
begin
process (clk,reset,sw1)
variable c :std_logic_vector(7 downto 0):="00000000";
variable counter :std_logic_vector(27 downto 
0):="0000000000000000000000000000";
begin
   if reset='1' then
        LED <= "00000000";
     elsif sw1='1' then
         LED <= "11111111";
     elsif(clk'event and clk='1') then
       counter := counter +1 ;
          if (counter ="1000000000000000000000000000") then
                c:=c+1;
                LED<=c;
             counter:="0000000000000000000000000000";
        end if;
    end if;
end process;
 
end Behavioral;
 
Last edited by a moderator:

I dont really see the problem. Its perfectly legal VHDL. What exactly is the problem?
Whats the clock frequency?

Another note - why are you using variables? do you realised that you are checking the non-registered version of C and counter? As a beginner, I would forget about variable for now and stick with signals.
 


i write this code no warning and error exist but in ISIM simulator LED don't ++

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity newv is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           sw1 : in  STD_LOGIC;
			  LED : out  STD_LOGIC_VECTOR (7 downto 0));
end newv;

architecture Behavioral of newv is
signal c :std_logic_vector(7 downto 0);
signal counter :std_logic_vector(4 downto 0):="00000";
begin

process (clk,reset,sw1)
--variable c :std_logic_vector(7 downto 0);
--variable counter :std_logic_vector(4 downto 0):="00000";
begin
 if (clk'event and clk='1') then
       if  reset='1' then
	        LED <= "00000000";
       elsif sw1='1' then
           LED <= "11111111";
	    else
			 counter <= counter+1 ;
	          if (counter = "10000") then
		  	    	   c <=c+1;      
  			 	      LED<= c;
		            counter <= "00000";
             end if;
 
	    end if;
 end if;
end process;	
end Behavioral;
 

Everything is working good but the only problem is you didnt initialized the signal C..

I attached the simulated code and result


Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity newv is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           sw1 : in  STD_LOGIC;
              LED : out  STD_LOGIC_VECTOR (7 downto 0));
end newv;
 
architecture Behavioral of newv is
signal c :std_logic_vector(7 downto 0);
signal counter :std_logic_vector(4 downto 0):="00000";
begin
 
process (clk,reset,sw1)
--variable c :std_logic_vector(7 downto 0);
--variable counter :std_logic_vector(4 downto 0):="00000";
begin
 if (clk'event and clk='1') then
       if  reset='1' then
            LED <= "00000000";
            c <= "00000000";
            
       elsif sw1='1' then
           LED <= "11111111";
        else
             counter <= counter+1 ;
              if (counter = "10000") then
                       c <=c+1;      
                      LED<= c;
                    counter <= "00000";
             end if;
 
        end if;
 end if;
end process;    
end Behavioral;
 
Last edited by a moderator:

mohammadmother said:
i write a vhdl code that is nearly accurate counter
every 1.34 s the LED will be ++
(2^27*10ns = 1.34 s )
Click to expand...
I find it interesting that nobody else has pointed out that to count for 2^27 you should use a 27-bit value and not a 28-bit value:
Code: 
variable counter :std_logic_vector(27 downto 0):="0000000000000000000000000000";

The following actually makes this rollover at (2^27)+1:
Code: 
if (counter ="1000000000000000000000000000") then
  counter <="0000000000000000000000000000";
end if;

You should actually count from "000000000000000000000000000" to "111111111111111111111111111", which means you don't even need to compare the count value to rollover as it will just rollover on it's own. To detect the point at which you rollover, you want to perform a reduction AND operation on the all 1's condition or compare the count to the all 1's condition.

If the intent was to do something clever with using the MSB to rollover the counter then you should instead do something like this:
Code: 
if (counter(27) = "1") then
  counter <= "0000000000000000000000000001";
else
  counter <= counter + 1;
end if;

Regards
 
Last edited:

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