dr pepper
Advanced Member level 1
I threw this circuit together, my intention being to generate a stable clock signal using the carrier o/p on pin 7, using a radio stations carrier.
I didnt have a dual gate fet so I used a J113, it works.
I dont get how the fet is connected to the '602 via C2 and C3, with the source and drain resistors being very different wont the signal levels be unbalanced?, doesnt make sense for an i/p thats sposed to be balanced.
The circuit works better than expected, I made some alterations on the front end so it can be used in a shipping container with an external active whip aerial.
I didnt have a dual gate fet so I used a J113, it works.
I dont get how the fet is connected to the '602 via C2 and C3, with the source and drain resistors being very different wont the signal levels be unbalanced?, doesnt make sense for an i/p thats sposed to be balanced.
The circuit works better than expected, I made some alterations on the front end so it can be used in a shipping container with an external active whip aerial.