Yikun
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I have installed NCSU FreePDK45 design kit for Cadence IC615 but have problem instantiating device layout with the following warning.
*WARNING* (DB-220704): The Pcell super master: NCSU_TechLib_FreePDK45/nmos_vtl/layout is not a SKILL super master. The usage of non-SKILL Pcells in Virtuoso is not a supported feature.
I can only see a white box with cross of the device instance in layout but when I open the layout view of the device itself, it is visible with correct metal layers.
I followed the Setup Files section of the following link to install the kit with correct paths:
https://www.eda.ncsu.edu/wiki/FreePDK45:Manual
and for P-Cells I have installed 64-bit PyCell Studio from Synopsys using instructions from the following link:
https://www.eda.ncsu.edu/wiki/FreePDK45:Using_P-Cells
*WARNING* (DB-220704): The Pcell super master: NCSU_TechLib_FreePDK45/nmos_vtl/layout is not a SKILL super master. The usage of non-SKILL Pcells in Virtuoso is not a supported feature.
I can only see a white box with cross of the device instance in layout but when I open the layout view of the device itself, it is visible with correct metal layers.
I followed the Setup Files section of the following link to install the kit with correct paths:
https://www.eda.ncsu.edu/wiki/FreePDK45:Manual
and for P-Cells I have installed 64-bit PyCell Studio from Synopsys using instructions from the following link:
https://www.eda.ncsu.edu/wiki/FreePDK45:Using_P-Cells