NCO timing issue, VERILOG fpga

module NCO_chipRate(sysclk, reset, cntl_word, chip_enable, nextChip, nco_val, get_nco_val);

	input sysclk, reset;
	input [31:0] cntl_word;
	input get_nco_val;
	
	output reg [2:0]chip_enable; //[2]late, [1]prompt,[0]early
	output reg [31:0]nco_val;
	output reg nextChip;
	
	reg   [29:0] accum_reg;
   reg   [20:0] cycle_count_reg;
   wire  [3:0] phase_key;
   wire  [31:0] accum_sum;
   wire	accum_carry;
   wire  [31:0] combined_carr_value;
	
	// 30 bit phase accumulator
   always @ (posedge sysclk)
	begin
		if (reset) accum_reg <= 0;
		else accum_reg <= accum_sum[29:0];
	end

	// cycle counter and value latching
   always @ (posedge sysclk)
   begin
		if (reset) cycle_count_reg = 0;
		else if (get_nco_val)
		begin
			nco_val = combined_carr_value; // latch in carrier value, then...
			cycle_count_reg = 0; // reset counter
		end
		else if (accum_carry) 
		begin
			cycle_count_reg = cycle_count_reg + 1'b1;
		end
	end
	
	assign accum_sum = accum_reg + cntl_word;
	assign accum_carry = accum_sum[30];
	assign phase_key = accum_sum[29:26];
	assign combined_carr_value[9:0] = accum_reg[29:20];
	assign combined_carr_value[31:10] = cycle_count_reg;
   
	always @ (posedge sysclk)
	begin
		if(phase_key == 4'd8)
		begin
			chip_enable[0] <= 0;
			chip_enable[1] <= 1;
			chip_enable[2] <= 0;
		end
		else if(phase_key == 4'd4)
		begin
			chip_enable[0] <= 1;
			chip_enable[1] <= 0;
			chip_enable[2] <= 0;
		end
		else if(phase_key == 4'd12)
		begin
			chip_enable[0] <= 0;
			chip_enable[1] <= 0;
			chip_enable[2] <= 1;
		end
		else
		begin
			chip_enable[0] <= 0;
			chip_enable[1] <= 0;
			chip_enable[2] <= 0;
		end
		
		if(phase_key == 4'd0) nextChip <= 1; //signal to advance chip coder
		else nextChip <= 0;
	end

endmodule

freq = controlword * 2^numberbits / clockfreq