NC verilog schematic to verilog

[jiminization]

I am using the Virtuoso NC-Verilog to convert my schematic to a verilog netlist. However, some of my instance name were renamed.
It uses the prefix "Inst_" instead of the name in the schematic. This causes some errors when I apply the sdf in this netlist.
How can I retain the name in the schematic? Thank you

 

[ThisIsNotSam]

I am using the Virtuoso NC-Verilog to convert my schematic to a verilog netlist. However, some of my instance name were renamed.
It uses the prefix "Inst_" instead of the name in the schematic. This causes some errors when I apply the sdf in this netlist.
How can I retain the name in the schematic? Thank you

You can always rely on an external tool to do a search and replace, perhaps with regex even.