NC-Sim VHDL simulation error: F,TOOMNS: more than one simulation name

[nanako]

I'm running some VHDL simulation with NC-Sim and I encountered the following error. As I'm pretty new to using NC-Sim for VHDL, can anyone tell me what's the error message actually mean and how to resolve it.

ncsim: 05.30-s005: (c) Copyright 1995-2004 Cadence Design Systems, Inc.
ncsim: *F,TOOMNS: more than one simulation name.

 

[nand_gates]

ncsim commands

Hi,
I got ur problem... What ur doing is you are giving more than one module
name to ncsim. You are only suppose to give top level module name to ncsim.

ncsim module1 module2 <--- wrong

ncsim top_module <--- correct

 

[nanako]

ncsim more than one simulation name

i believe i only have 1 module in the ncsim command. here is what i did.

1. ncvhdl abc.vhd

2. ncelab 'TESTBENCH.TOP:ABC'

3. ncsim 'TESTBENCH.TOP:ABC'

inside the abc.vhd file i have

entity top is
.....
end top;

architecture abc of top is
.....
end abc

 

[nand_gates]

vhdl convert std_logic_vector to string

Hi you try out this example.....it runs without any problem on my side!

--
-- This cds.lib file 
--
DEFINE ieee   /opt/cadence-ius5.3/tools/inca/files/IEEE
DEFINE std    /opt/cadence-ius5.3/tools/inca/files/STD
DEFINE synopsys /opt/cadence-ius5.3/tools/inca/files/SYNOPSYS
DEFINE vhdl ./vhdl

--
--This is hdl.var file
--
DEFINE WORK vhdl

counter.vhd file

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity counter is
  port (
    clk   : in  std_logic;
    reset : in  std_logic;
    count : out std_logic_vector(7 downto 0));
end counter;

architecture behave of counter is
signal count_int : std_logic_vector(7 downto 0);
begin  -- behave

  counting : process (clk, reset)
  begin  -- process count
    if reset = '0' then                 -- asynchronous reset (active low)
      count_int <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      count_int <= count_int + "00000001";
    end if;
  end process counting;
count <= count_int;
end behave;

count_tst.vhd file

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity count_tst is

end count_tst;
architecture my_test of count_tst is
component counter
    port (
    clk   : in  std_logic;
    reset : in  std_logic;
    count : out std_logic_vector(7 downto 0));
end component;
signal clk   : std_logic := '0';
signal reset : std_logic := '0';  
signal countval : std_logic_vector(7 downto 0);
--
-- convert a std_logic value to a character
--
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
  'U' => 'U',
  'X' => 'X',
  '0' => '0',
  '1' => '1',
  'Z' => 'Z',
  'W' => 'W',
  'L' => 'L',
  'H' => 'H',
  '-' => '-');
--
-- convert a std_logic_vector to a string
--
function to_string(inp : std_logic_vector)
  return string
is
  alias vec : std_logic_vector(1 to inp'length) is inp;
  variable result : string(vec'range);
begin
  for i in vec'range loop
    result(i) := to_char(vec(i));
  end loop;
  return result;
end;

begin  -- my_test
  u1 : counter
    port map (
      clk   => clk,
      reset => reset,
      count => countval);

    testing: process
    begin  -- process testing
      wait for 23 ns;
      reset <= '1';
      wait for 200 ns;
      wait;
    end process testing;

clk <= transport not clk after 5 ns;
  process (clk)
  begin  -- process
    if clk'event and clk = '1' then  -- rising clock edge
      assert false report "count = "&to_string(countval) severity note;
    end if;
  end process;    
end my_test;

Here are the commands to compile and run

1. ncvhdl counter.vhd count_tst.vhd
2. ncelab vhdl.count_tst:my_test
3. ncsim vhdl.count_tst:my_test

Hope this helps

 

[nanako]

ncsim ieee library

the example works well for me. just that the design that i have is more complex. i also discover that in the abc.vhd file, there are a few other entity too, like memory modules, uart, etc... wonder how that affect. i ran the simulation in the original site, everything works fine and when i bring over to my env the error came it.