the unused input pins for cmos/ttl should tie it to ground and the lvds input pins should let it float (there should be fail-safe).
there operating frequency for this device is 20-85MHz, the pll won't work, difficult to lock, below 10MHz or over 100MHz.
check your current consumption of the chip
check the output of the lvds driver, both clock and data
make sure you have 100Ohm termination on the receiver side
what is your loading? don't exceed 5p....that's difficult.
pwdn' should be high