NANOSIM - VCS : use_spice

[tok47]

Hi ALL,


Anyone use this command before "use_spice -cell" ?

If let say I have this " use_spice -cell testchip_A".

Is it the tool will choose all the entire ckt and sub-ckt in testchip_A will be SPICE?

Thanks


Tok

 

[ankitgarg0312]

as per my understanding

if u specify command use_spice -cell testckt

then ns-vcs will assume all testckt is in spice.

if u have some parts of testckt block in verilog ( dough nut partitioning)
e.g u have inv and buf inside testckt where inv is spice and buf is verilog

then u must specify
use_verilog -module buf

while creating simv , ns-vcs parser will partition design in spice and verilog depending upon use_spice and use_verilog commands.

hope this helps!!

 

[tok47]

how about i have some other blocks which I have VERILOG and also SPICE?

Let say, I have Instance A with VERILOG and also SPICE in Circuit TESTCKT.

If I "use_spice -cell TESTCKT"

Will Instance A selected as VERILOG or SPICE?

Thanks

Tok

 

[ankitgarg0312]

while creating simv all decision are done , which one to be used for spice and which one for verlog...

if u have declared testckt as spice , and some internal blocks u have both in spice and verilog
cosim will take spice defination in that case.
use_verilog command will force to take verilog equivalent of same

u can easily make small testcase to verify above,
check simv.msv/interface_element.rpt file.... and hierarchy.rpt

these file clearly identifies boundry elements and used model for each block...

also check "Mixed-Signal Simulation User Guide"
download from solvnet ..
it has all details on commands and usage

 

[tok47]

Thanks alot.