Hi all,
I have some problem when I use the ns_vcs tool.
Q1.
I am able to simulate the whole chip including digital and analog part, so I think the flow is correct.
There is a spice mode of SRAM in my design, it takes a lot of time to simulate.
I want to accelerate the simulation by using hierarchical array reduction (HAR) in nanosim.
I try it when only using nanosim to simulate the SRAM, it is work.
But I use it in the ns_vcs tool (added define_har_corecell into cfg and -har in vcsAD.init), there is an error message "VCS runtime internal error (core dumped)".
Did I do anything wrong or the feature cannot be used in ns_vcs?
Q2.
https://i.imgur.com/Mk0UwQG.png
As the figure shown, this is a part of the cosimulation waveform.
The light blue waveform is the output of analog circuit, and the waveform at the bottom is it transfer to logic value.
As you see, the light blue one is like a square wave, but after the transfer it is like a step wave instead of square.
Can anyone tell me how did this happen?
I am not a native speakers of english, so I am sorry about if there are errors in the article.