nano-CMOS circuits and physical design

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arghpok

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The gate dielectric thickness is approaching atomic dimensions and at 1.2 nm in the 90nm node is about five atomic layers of oxide. If you look at the figure you'll see that gate oxide scaling is slowing as it approaches the limit, which is one atomic layer thick. The points is, ¿ anybody does know about any transistor model which take into account the effects of such physical restriction pretty viewable here like gate leakage current ?

and, ¿ Which are the new materials for the gate and how they increase the process costs ?

[/img]http://rapidshare.com/files/19073567/fig1p1.GIF.html
 

I'm by far no expert on simulation models, but I can tell you that new gate stacks for >=45nm are based on hafnium oxides and metal gates with engineered work- functions for nmos and pmos. Both work- function engineering and totally new hafnium oxides in combination with low-k dielectrics (!) and litho challenges (IBM just announced to use immersion litho for their 45nm node to come Q4!) are the driving forces regarding cost in new tech nodes.

Hope that helps.

C.
 
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