[SOLVED] NAND gates are faster?

Hello,

I’m designing one full bridge with drivers to control one powerful motor (200W).

I want to implement the brake function with logic gates but I suppose that the time delay in de gates can be important. The question is: what type of circuit is more fast? The yellow or the green circuit (see attached PDF)? I heart long time ago that the NAND gates have one of the best performances.

PWM and BRAKE are the inputs and A, B, C and D are the outputs to the MOSFET drivers.

Any suggestions?

Thanks!

Please check below link:
https://allthingsvlsi.wordpress.com...based-design-is-better-than-nor-based-design/

kkdelabaca said:

Hello,

I’m designing one full bridge with drivers to control one powerful motor (200W).

I want to implement the brake function with logic gates but I suppose that the time delay in de gates can be important. The question is: what type of circuit is more fast? The yellow or the green circuit (see attached PDF)? I heart long time ago that the NAND gates have one of the best performances.

PWM and BRAKE are the inputs and A, B, C and D are the outputs to the MOSFET drivers.

Any suggestions?

Thanks!

Click to expand...

In an FPGA both circuits will fit in exactly one LUT so it doesn't matter which you use as they will have the exact same delay.

Now ignoring the fact that you posted this in the programmable logic section...probably more appropriate to post this in the Electronics Elementary Questions section.

Get the data sheet for the NAND2, AND, and INV gates and add up the gate delays for the worst case delay through the longest path for both circuits. As you have 4 gate delays in the NAND circuit and 3 gate delays in the AND circuit I would guess the AND circuit is probably faster.




In a NXP HCT00 (NAND) tpd = 24 ns (max) @ 4.5V 85C
HCT04 (INV) tpd = 24 ns (max) @ 4.5V 85C
HCT08 (AND) tpc = 30 ns (max) @ 4.5V 85C

So NAND circuit:
24 *4 = 96 ns

AND circuit:
2 * 24 + 30 = 78 ns

Regards

Choice of supply voltage, drive current, load capacitance, logic family and temperature all affect speed much more than the choice of NAND, AND, & INV.

Comparing one family, 74LVC2Gxx from NXP over temp and voltage (-40 'C to +85 'C, 4,5~5.5V), we get;

AND 74LVC2G08 tpd=0.5~3.8ns
INV 74LVC2G04 tpd=1 ~ 3.2ns (3 stages)
INV 74LVC1GU04 tpd=0.5~3.2ns (1 stage=unbuffered)
NAND 74LVC2G08 tpd=1 ~ 3.5ns
NOR 74LVC2G02 tpd=0.6~4.3ns

Due to low capacitance and path length , tpd of internal stages are faster than last stage complementary driver in IC specs.

Typically AND, NAND, OR, NOR use the fastest configuration with lowest output impedance inverter as a buffer.
so AND= 2INV+2NOR+INV+INV
AND 74LVC2G08

& NAND=2INV+2NOR+INV


& OR =2INV+2NAND+INV+INV

& NOR =2INV+2NAND+INV

NOR 74LVC2G02

Conclusion: This means you can't design a motor controller from simple logic. You must start with Motor Specs for V, Ip, Iavg, assuming Ip is for peak acceleration and braking is based on coil resistance. Then you need driver specs and power supply specs. The ESR of each component and timing from L to H to L skew are critical to prevent shoot thru. Then you need to specify some Protection requirements and ambient for voltage current and temperature.

Thanks all for your Help!! Is an authentic pleasure write in this forum.

Finally I will choose fast logic gates @5V and the delay in the gates will be miserable compared with the typical delay of the mosfet driver (about 170ns in the IRS2186).

I see in www.ti.com that one of the faster family @5V is the "S" family (for example SN74S04 and SN74S08).

The 74S is the Schottky TTL version is still not as fast as the 74LVC2 CMOS family example I used. But a few ns more won't matter as long as you start with the design approach, that I recommended, then you can determine how much dead-time for both commutation and changing directions to avoid over heating.

In braking you are shorting out the stored inertial energy in the motor now acting as a generator shorted to ground across the Bridge switches. This rate can be controlled with PWM in both directions if there is a lot of inertial load and extended surge time.

Yes! :thumbsup: LVC is faster, the problem is that this family don't have devices in SOIC packages