Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

n-depletion MOS reliability issue.

Status
Not open for further replies.

naisare

Member level 2
Member level 2
Joined
Oct 18, 2004
Messages
43
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,288
Activity points
391
I am using an n-depletion mosfet whose Vt is -0.5V.
This mos has to be in off condition during the normal operation of the chip.
So i connect the gate to -2V and when it has to be ON, I connect the gate to 0V.
It works fine. But the drain of this MOS is connected to supply voltage 5V.
Now, the voltage difference between the gate and drain is 7V during most of the chip operation time.
This creates the releability issue for this MOS. How to make this voltage difference lower(max 5V)
Since the source of the MOS is connected to output of the chip, I cant add any resistance between
the drain and supply voltage(functionality problem).
any help?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top