N^2 function implementation

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ivlsi

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Hi All,

What's the optimal implementation of N^2 function using a pure or registered logic? I mean flops, shift registers, logic gates, etc...

Thank you!
 

yes. what's its optimal implementation? the implementation should be simpler that a regular multiplier... what's the trick in the implementation?
 

Did you ever try multiply in binary system? Try multiply number two by itself. And now number four...

It isn't a test, just try look at it through a binary system glasses.
 

As generally as phrased, the original question seems to ask for re-telling of a digital design text book's chapter. Optimal in which sense, speed or area, is a sequential squarer acceptable, etc.?

Edaboard is my easygoing Google?

the implementation should be simpler that a regular multiplier... what's the trick in the implementation?
Click to expand...
You're basically right. There's some saving for a squarer versus a full multiplier in logic cells. Personally, I leave multiplier and squarer implementation to available vendor IP. Thus I can't help you with the details.
 

As for the squarer implementation, should it be so complex design so that it's patent protected and special dedicated IPs were created?
 

As others, I'm using the term vendor IP for all code libraries provided by hardware or software tool vendors, not only protected IP. E.g. integer and floating point arithmetic libraries shipped with FPGA synthesis tools.
 

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