My VHDL Code is giving unexpected value after simulating with Floating point IP cores

[Soh_bhat]

Hi,
I am working on a project where I am using some IP cores of floating point with latency 3. What I am doing is there is some specified value of x_in, y_in, h, p_in, p1_in, c_in and it will do the operations using a module that has some floating point operation. The first iteration is coming as expected. Point is the x_out and y_out value of the first iteration will be stored as the next iteration's x_in and y_in and generate the result. The storing is happening but it is not giving the expected output from the second one onwards. Don't know if I am writing the test bench wrong. Please let me know. But the values come with latency 0 as it has no clock. Please check the test bench along with the waveform.
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/26/2023 08:02:34 PM
-- Design Name:
-- Module Name: Top_TB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Top_TB is
-- Port ( );
end Top_TB;

architecture Behavioral of Top_TB is
component Top is
Port (
clock: in std_logic;
inst: in std_logic_vector(31 downto 0);
cont: out std_logic_vector(31 downto 0);
addr: out std_logic_vector(11 downto 0);
x_out: out std_logic_vector(31 downto 0);
y_out: out std_logic_vector(31 downto 0);
x_in: out STD_LOGIC_VECTOR(31 downto 0);
y_in : out STD_LOGIC_VECTOR(31 downto 0);
h : out STD_LOGIC_VECTOR(31 downto 0);
p_in : out STD_LOGIC_VECTOR(31 downto 0);
p1_in : out STD_LOGIC_VECTOR(31 downto 0);
c_in : out STD_LOGIC_VECTOR(31 downto 0);
initial_flag: out std_logic;
-- init_flag: in std_logic;
initial: out std_logic;
cma_out: inout std_logic_vector(11 downto 0)

);
end component;

signal clock: std_logic := '0';
signal cont: std_logic_vector(31 downto 0);
signal inst: std_logic_vector(31 downto 0);
signal addr : std_logic_vector(11 downto 0);
signal initial_flag: std_logic;
signal x_in: STD_LOGIC_VECTOR(31 downto 0);
signal y_in : STD_LOGIC_VECTOR(31 downto 0);
signal h : STD_LOGIC_VECTOR(31 downto 0);
signal p_in : STD_LOGIC_VECTOR(31 downto 0);
signal p1_in : STD_LOGIC_VECTOR(31 downto 0);
signal c_in : STD_LOGIC_VECTOR(31 downto 0);
signal initial: std_logic;
signal cma_out: std_logic_vector(11 downto 0);
signal x_out: STD_LOGIC_VECTOR(31 downto 0);
signal y_out : STD_LOGIC_VECTOR(31 downto 0);
constant clock_period : time := 10 ns;



begin

uut: Top port map (
clock => clock,
inst => inst,
initial_flag => initial_flag,
cont => cont,
addr => addr,
x_in => x_in,
y_in => y_in,
h => h,
c_in => c_in,
p_in => p_in,
p1_in => p1_in,
initial => initial,
x_out => x_out,
y_out => y_out,
cma_out => cma_out
);

clk_process rocess
begin

clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;

end process clk_process;

proc: process
begin

--write_en <= '1';

inst <= "000000000000" & "00001" & "000" & "00000" & "0001100";
wait for clock_period;

--write_en <= '1';

inst <= "000000000100" & "00010" & "000" & "00000" & "0001100";
wait for clock_period;

--write_en <= '1';

inst <= "000000001000" & "00011" & "000" & "00000" & "0001100";
wait for clock_period;

--write_en <= '1';

inst <= "000000001100" & "00100" & "000" & "00000" & "0001100";
wait for clock_period;

--write_en <= '1';

inst <= "000000010000" & "00101" & "000" & "00000" & "0001100";
wait for clock_period;

--write_en <= '1';

inst <= "000000010100" & "00110" & "000" & "00000" & "0001100";
wait for clock_period;


--wait for clock_period * 50.5;

inst <= "000000000000" & "00001" & "101" & "00000" & "0001100";
wait for clock_period * 45;


--wait for clock_period * 14;

--wait for clock_period * 51;
inst <= "000000000000" & "00001" & "001" & "00000" & "0001100";

wait for clock_period;



inst <= "000000000000" & "00001" & "100" & "00000" & "0001100";
wait for clock_period;

wait;

end process;
end Behavioral;

Please help.

 

[kaz1]

You are driving clock input but you say there is no clock. What do you mean?
You got single data input 'inst' and you are driving it with some values.
You got one inout cma_out but is left undriven as input.

so the testbench inputs looks ok apart from cma_out.
Any other issues is for you to check as no body has visibility to your design.
I normally avoid inout ports for FPGAs as it could complicate it on you

 

[Soh_bhat]

So, you are telling to check for the cma only?

 

[kaz1]

So, you are telling to check for the cma only?

From testbench input perspective all inputs need to be cared for.
Whether your issue is cma or not I can't tell. It depends what is it meant for as input.

 

[FvM]

I see several problems.
1. Clocking has been already mentioned. I would expect that clock is generated in the testbench and that stimuli are synchronized with clock, e.g. by edge sensitive statements. That's apparently not happening.
2. The port specification and configuration of the float IP core is unknown. There should be link to the documentation.
3.The intended operation is unclear.

 

[Soh_bhat]

I have created a module in which I have connected ports of that with the documentation of IP and it is running correctly with the test bench of that module. In the top module, I instantiated all the ports with the other modules and want to see the results based on that module. Can you check my memory file? Interesting matter is that with latency 0, it is giving me the result as it has no clock generation with latency 0. Whenever I m taking clock, it is giving me unknown outputs. Please check my memory file:

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/26/2023 07:31:54 PM
-- Design Name:
-- Module Name: Mem - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE. numeric_std. ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mem is
Port (
cont: in std_logic_vector(31 downto 0);
addr : in std_logic_vector(11 downto 0);
x_in: out STD_LOGIC_VECTOR(31 downto 0);
y_in : out STD_LOGIC_VECTOR(31 downto 0);
h : out STD_LOGIC_VECTOR(31 downto 0);
p_in : out STD_LOGIC_VECTOR(31 downto 0);
p1_in : out STD_LOGIC_VECTOR(31 downto 0);
c_in : out STD_LOGIC_VECTOR(31 downto 0);
write_en: in std_logic;
clock: in std_logic;
flush : in std_logic;
x_out: in STD_LOGIC_VECTOR(31 downto 0);
y_out : in STD_LOGIC_VECTOR(31 downto 0);
init_flag: in std_logic ;
init: in std_logic;
--cma_in: in STD_LOGIC_VECTOR(11 downto 0);
cma_out: inout STD_LOGIC_VECTOR(11 downto 0) );
end Mem;

architecture Behavioral of Mem is
type mem_type is array (0 to 127 ) of std_logic_vector (31 downto 0);

signal mem: mem_type;
signal cma_in: STD_LOGIC_VECTOR(11 downto 0) := "000000011000";
signal cma_next: STD_LOGIC_VECTOR(11 downto 0) ;
signal cma_Var: STD_LOGIC_VECTOR(11 downto 0);
constant clk_period: time := 10 ns;

-- signal cma_x_val, cma_y_val: STD_LOGIC_VECTOR(31 downto 0);


begin
process(clock, write_en, flush, init_flag, cma_in)
begin
--RKI
if ((write_en = '1') and (flush = '0')) and (init_flag = '1') and rising_edge(clock) then
mem(TO_INTEGER(unsigned(addr))) <= cont;
end if;


--end process;




if flush = '1' and write_en = '0' and rising_edge(clock) and init = '0' then --- FLUSH MODE
x_in <= mem(0);
y_in <= mem(4) ;
h <= mem(8);
p_in <= mem(12);
p1_in <= mem(16);
c_in <= mem(20);

end if;

--end process;

--process(clock, write_en, flush)
--begin
-- cma_val <= mem(to_integer(unsigned(cma_in)));
-- cma_next_val <= mem(to_integer(unsigned(cma_next)));

if flush = '0' and write_en = '1' and rising_edge(clock) and (init_flag = '0') and init = '1' then

-- if to_integer(unsigned(cma_in)) >= 24 then
-- x_in <= mem(to_integer(unsigned(cma_in)) - 8);
-- y_in <= mem(to_integer(unsigned(cma_in)) - 4) ;

-- end if;

if to_integer(unsigned(cma_in)) >= 32 then
x_in <= mem(to_integer(unsigned(cma_in)) - 8);
y_in <= mem(to_integer(unsigned(cma_in)) - 4) ;

end if;

mem(0) <= x_out;
-- y_cont <= y_out;
--y_in <= y_out;
mem(4) <= y_out;


mem(to_integer(unsigned(cma_in))) <= x_out;

cma_next <= std_logic_vector(unsigned(cma_in) + 4);
mem(to_integer(unsigned(cma_next))) <= y_out ;

cma_out <= std_logic_vector(unsigned(cma_in) + 8);



cma_in <= cma_out;




-- cma_out <= cma_in; ---32 <= 24
-- cma_in <= cma_next;




end if;
--end if;
end process;







end Behavioral;

Please reply.

--- Updated Apr 1, 2023 ---

I see several problems.
1. Clocking has been already mentioned. I would expect that clock is generated in the testbench and that stimuli are synchronized with clock, e.g. by edge sensitive statements. That's apparently not happening.
2. The port specification and configuration of the float IP core is unknown. There should be link to the documentation.
3.The intended operation is unclear.

Can you help me with the modification in test bench for your first statement?