My Layout is not maintaning the Phase Margin

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hardyboy_86

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hi,
i am new analog layout engineer, the problem i am facing in my layout is with the phase margins and gain margins, the designer is not satisfied the phase and gain margins of my circuit, please let me know what precautions should i follow to minimize these errors.
 


The mentioned properties of your amplifier (stability margins too small) are no "errors".
Each amplifier designed to operate with external feedback needs a certain "distance" to the stablity limit in case of 100% feedback.
This distance is expressed as phase and gain margin (given in degree and dB, respectively).
At least one of both margins (mostly the phase margin) is given as a design requirement.
Thus - what are your requirements ? What kind of amplfier are you designing?
 
Did you simulate phase margin and gain margin in pre-layout netlist and in post-layout netlist? How are the simulation results?
 
Yes before simulation all results are fine but after post layout simulation the designer told me that my layout is not satisfying the phase and around 20 degree phase is decreasing.
 

One common mistake when designing an amplifier is using too small of a compensation capacitor (Cc) within the amplifier. I assume you are designing a two stage design, thus if your Cc was made small, lets say you in 90nm CMOS and you use a Cc =10-50fF, which I have seen before (a bad design), this is in the range of the parasitics which will be created within the amplifier when doing the layout, thus you won't pole split anymore since all your pole are shifting in. A rule of thumb is 5 to 6X calculated parasitics on a node is a good Cc cap size. If this isn't your problem, maybe posting your schematic might help.

Hope this helps.

JGK
 
If the designer is satisfied with his simulations pre layout, but not with the extracted layout, then what you are facing are mismatches and parasitics. typically layout engineers layout half an amplifier then copy mir it for the other half, this ensures symmetry(which helps eliminate mismatch), to reduce parasitic loading you need to make sure you do not have sensitive nets running over or next to other nets, ie increase dead space around them, and keep the runs short.

-Pb
 
hardyboy_86 said:
Yes before simulation all results are fine but after post layout simulation the designer told me that my layout is not satisfying the phase and around 20 degree phase is decreasing.
Click to expand...

Could be mismatch created by unsymmetric layout (easy to check) or parasitics. In the post-layout netlist every node will have an additional parasitic capacitor. Some nodes in the signal path input->output are very relevant for phase margin. I think this is the basic starting point for this analysis: Do you understand the circuit function sufficiently that you know which nodes' parasitics are most relevant for phase margin? I think this part is not only the layout engineer's job: The designer should know it better and tell the layout engineer which nodes' parasitics are critical, and which device groups need best matching, so that he can take care of it when creating the layout.
 
Thank you so much,, i have pretty much figured out the problem by changing the capacitive sensitive nodes to higher metals as higher metals have low cap/sq value. and also i have routed those nodes in a very calculated manner which helped me to get the phase difference from 22 to 10 degrees.
 

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