My error ,any one slove this

Hi Experts,

When i synthesis one of my module in xilinx, i am getting this error , i don't know how to resolve this ,any one help me.

This is my Code


`include "rVEX_pkg.v"
//use work.ctrl_operations.all;

module c(clk,reset,opcode,pc,lr,sp,offset,br,in_valid,pc_goto,result,out_valid);

input clk; // system clock
input reset; // system reset
input [6:0] opcode; // CTRL opcode
input [(`ADDR_WIDTH - 1) : 0] pc; // current program counter
input [31:0] lr; // current link register ($r0.63) contents
input [31:0] sp; // current stack pointer ($r0.1) contents
input [(`BROFF_WIDTH - 1) : 0]offset; // branch offset (imm or lr) value
input br; // branch register contents
input in_valid; // '1' input is valud

output wire [(`ADDR_WIDTH - 1) : 0] pc_goto; // address to jump to
output wire [31:0] result; // new lr or sp value
output reg out_valid; // '1' output is valid



reg [31:0] result_i;
reg [(`ADDR_WIDTH - 1) : 0]pc_goto_i ;


assign result = result_i;
assign pc_goto = pc_goto_i;


function [(`BROFF_WIDTH - 1) : 0] f_GOTO;
input [(`BROFF_WIDTH - 1) : 0] offset;
begin
f_GOTO=offset[(`ADDR_WIDTH - 1) : 0];
end
endfunction

function [31:0] f_IGOTO;
input [31:0] lr;

begin
f_IGOTO=lr[(`ADDR_WIDTH - 1) : 0];
end
endfunction

task f_CALL;
input [(`BROFF_WIDTH - 1) : 0] offset;
input [(`ADDR_WIDTH - 1) : 0] pc;
output [(`ADDR_WIDTH - 1) : 0] pc_goto;
output [31:0] result;
reg [31:0] pc_tmp;
begin
pc_tmp[(`ADDR_WIDTH - 1) : 0] = pc;
pc_goto = offset[(`ADDR_WIDTH - 1) : 0];
result = pc_tmp + 1;
end
endtask

task f_ICALL;
input [31:0] lr;
input [(`ADDR_WIDTH - 1) : 0] pc;
output [(`ADDR_WIDTH - 1) : 0] pc_goto;
output [31:0] result;
reg [31:0] pc_tmp;
begin
pc_tmp[(`ADDR_WIDTH - 1) : 0] = pc;
pc_goto = lr[(`ADDR_WIDTH - 1) : 0];
result = pc_tmp + 1;
end
endtask

function [(`ADDR_WIDTH - 1) : 0] f_BR;
input [(`BROFF_WIDTH - 1) : 0] offset;
input [(`ADDR_WIDTH - 1) : 0] pc;
input br;
begin
if (br ==1'b1)
f_BR= offset[(`ADDR_WIDTH - 1) : 0];
else
f_BR=(pc + 1);
end
endfunction

function [(`ADDR_WIDTH - 1) : 0] f_BRF;
input [(`BROFF_WIDTH - 1) : 0 ] offset;
input [(`ADDR_WIDTH - 1) : 0] pc;
input br;
begin
if (br ==1'b0)
f_BRF= offset[(`ADDR_WIDTH - 1) : 0];
else
f_BRF= (pc + 1);
end
endfunction

task f_RETURN;
input [(`BROFF_WIDTH - 1) : 0] offset;
input [31:0] lr;
input [31:0] sp;
output [(`ADDR_WIDTH - 1) : 0] pc_goto;
output [31:0] result;

begin
pc_goto = lr[(`ADDR_WIDTH - 1) : 0];
result = sp + offset;
end
endtask

// Controls CTRL operations
always @(posedge clk or posedge reset)
begin
if (reset) begin
out_valid = 1'b0;
result_i =32'b0;
pc_goto_i = {`ADDR_WIDTH{1'b0}}; end

else begin
if (in_valid) begin

out_valid = 1'b1; // this will be overriden a non-existent opcode is issued

case (opcode)

`CTRL_GOTO :

pc_goto_i = f_GOTO (offset);

`CTRL_IGOTO :

pc_goto_i = f_IGOTO (lr);

`CTRL_CALL :

f_CALL (offset, pc, pc_goto_i, result_i);

`CTRL_ICALL :

f_ICALL (lr, pc, pc_goto_i, result_i);

`CTRL_BR :

pc_goto_i = f_BR (offset, pc, br);

`CTRL_BRF :

pc_goto_i = f_BRF (offset, pc, br);

`CTRL_RETURN :

f_RETURN (offset, lr, sp, pc_goto_i, result_i);

`CTRL_RFI :

f_RETURN (offset, lr, sp, pc_goto_i, result_i);

`CTRL_XNOP :

pc_goto_i = {`ADDR_WIDTH{1'b0}};

`NOP :

pc_goto_i = {`ADDR_WIDTH{1'b0}};

default:

out_valid = 1'b0;

endcase end
else
out_valid =1'b0;
end
end
endmodule




my error

ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<31>> of logic node <result_i_mux0002<31>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<30>> of logic node <result_i_mux0002<30>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<29>> of logic node <result_i_mux0002<29>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<28>> of logic node <result_i_mux0002<28>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<27>> of logic node <result_i_mux0002<27>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<26>> of logic node <result_i_mux0002<26>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<25>> of logic node <result_i_mux0002<25>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<24>> of logic node <result_i_mux0002<24>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<23>> of logic node <result_i_mux0002<23>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<22>> of logic node <result_i_mux0002<22>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<21>> of logic node <result_i_mux0002<21>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<20>> of logic node <result_i_mux0002<20>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<19>> of logic node <result_i_mux0002<19>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<18>> of logic node <result_i_mux0002<18>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<17>> of logic node <result_i_mux0002<17>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<16>> of logic node <result_i_mux0002<16>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<15>> of logic node <result_i_mux0002<15>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<14>> of logic node <result_i_mux0002<14>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<13>> of logic node <result_i_mux0002<13>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<12>> of logic node <result_i_mux0002<12>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<11>> of logic node <result_i_mux0002<11>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<10>> of logic node <result_i_mux0002<10>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<9>> of logic node <result_i_mux0002<9>> has no source
ERROR:Xst:1706 - Unit <c>: port <result_i_concat0000<8>> of logic node <result_i_mux0002<8>> has no source
ERROR:Xst:1847 - Design checking failed


actually result_i is a 32 bit reg in my module.


--Kanimozhi.M

Check out the defines which you have used : `ADDR_WIDTH, `BROFF_WIDTH

For example if address width is 7, all u r tasks will return with zeros on MSB side and in the synthesis tool might have option set that all the constant flops will be removed for optimization. If you don't want to remove these flops, just change the option in the synthesis tool.

Thank u DCREDDY1980,

But i don't know how to change in the synthesis tool option.

--Kanimozhi

Added after 19 minutes:

Hi DCREDDY1980, Now the code is synthesized.

Thank U