my Circuit drawing current with no load

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bio_man

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Hi folks,

I build the attached circuit (it is a simple voltage doubler, Vou=2Vin). I used ring oscillator to generate 200kHz frequency (Phi1, Phi2 in the circuit) these two signals are non-overlapping. I got a perfect output voltage as expected. However, when I measure the input current, it seems my circuit always drawing current of around and it keeps increasing when I increase the input voltage. For example, with 0.5V input, the current is -17.6mA. This circuit is built for very low input voltage (ranges 0-1V)

I thought that the capacitors draw the current in charging, but they should hold the charge in steady state. I am using 2.2uF ceramic cap, I measured the voltage across the cap and it gave me almost dc voltage which I expect ideally. So, the caps are balanced and once they charged they keep their voltage!

Any ideas to share about this problem?

Also, one simple question, how can I measure the input impedance of my circuit? my sense this impedance is changing depends on the switching, Vin and other factors. Can I just measure the input with multi-meter while it is not powered?!
 

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leaky caps. Also what are your switches, if the timing over laps you'll get lose, but also can you be leaking from the switch to ground.
I'm assuming your using a analog switch. what are the rails of the switch in relation to your Vin?
 

Hi,

The oscillator needs power to run.
And it drives capacitive loads: traces, mosfet gate capacitance with it's miller capacitance.
All the charged energy needs to be dissipated as heat --> causing supply current

Klaus
 

KlausST said:
Hi,

The oscillator needs power to run.
And it drives capacitive loads: traces, mosfet gate capacitance with it's miller capacitance.
All the charged energy needs to be dissipated as heat --> causing supply current

Klaus
Click to expand...
The oscillator is powered by a USB cable connected to my laptop.

- - - Updated - - -

RobertFalbo said:
leaky caps. Also what are your switches, if the timing over laps you'll get lose, but also can you be leaking from the switch to ground.
I'm assuming your using a analog switch. what are the rails of the switch in relation to your Vin?
Click to expand...

I'm using nMos switches. What do mean by analog switches?

Regarding the voltage over the switch, they are around 2-3 multiples of Vin.

The clocks are non-overlapped and there is no shoot through states, that what made me questioning about drawing current in steady state
 

Hi,

Maybe it's time to show the real, complete circuit.
What ceramics type are the capacitors?

Klaus
 

KlausST said:
Hi,

Maybe it's time to show the real, complete circuit.
What ceramics type are the capacitors?

Klaus
Click to expand...

Hi Klaus,

I am ceramic caps from TKD, and small signal switches from infineon: their datasheets are attached. regarding the circuit, I am using the same as shown in previous pic with addition to ring oscillator and non-overlap clocks generator using 74HC04 hex inverter IC and 74HC00 NAND gates IC. They are all attached.

- - - Updated - - -

forgot to say, my ring oscillator generates 200kHz clock to drive the MOSFETS in the converter
 

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  • MOS_BSS816NW.pdf
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  • Cap_4700nF.pdf
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Hi,

With 1n at the AND gate outputs I expect rather slow rise and fall rate.
Can you show both clocks in one scope picture..
I can"t see how you ensure "non overlap" clocks.

Klaus
 

KlausST said:
Hi,

With 1n at the AND gate outputs I expect rather slow rise and fall rate.
Can you show both clocks in one scope picture..
I can"t see how you ensure "non overlap" clocks.

Klaus
Click to expand...

I am sorry Klaus for being late, just go a travel on the way!.

the clocks are attached. after The NANDs and without adding the 1nF caps, there was overlapping which is some I don't want. So, I placed the 1nF to slow down (add delays) to both of them and by that I got enough time for switching off (Sa transistors) before Sb transistors turn on.
 

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bio_man said:
clocks generator using 74HC04 hex inverter IC and 74HC00 NAND gates IC. They are all attached.
Click to expand...

You are using three gates from a hex inverter to make an oscillator. That part is fine.

You have not used an external R for adding a time constant; you are using internal delays and internal resistance to control the time constant. I do not like that.

At 200kHz that may not be the best idea.
 


Thanks c_mitra for your input. don't you think adding C is enough?
because my thinking to increase the delay, I need to increase R or C or both. So, I decided to increase C and also I am getting a nice 200kHz pulse. Would you please share with me why you think it is not good avoiding using R?
 

bio_man said:
Would you please share with me why you think it is not good avoiding using R?
Click to expand...

A capacitor just appears as a short to a voltage pulse- the current will be limited by internal circuit within the IC. The logic pins can source or sink only a finite current.

Without an R you do not know the time constant and your control over the circuit function is limited. The capacitor(s) charge and discharge with very large currents (true it is for a very short time).

Even a 1 Ohm resistor will improve both reliability and performance.
 


So you mean adding 1 ohm parallel to each 15nF cap between the inverters?
 

bio_man said:
So you mean adding 1 ohm parallel to each 15nF cap between the inverters?
Click to expand...

In this particular case, I believe you should add R in series with the C. Then you will not be depending on the internal source/ sink capacity of the IC.
 
Hi,

The series R should be at least 5 times the expected source impedance of the driver...to give reliable and calculable results.

Klaus
 
If you calculate the energy stored in the ring oscillator capacitors and multiply with 200 kHz, you'll know where the unwanted quiescent current comes from. A reasonable design would reduce the capacitor values at least by factor 100 and add respective series resistors to the gate outputs.

There will be still some quiescent current caused by the unavoidable Cgs and Cds of SC power switches.
 


And, imho, this may be the major source of inefficiency in the design.
 

Thanks all for your input. I think you focused on the Ring oscillator issue and forget about the main problem. The ring oscillator and control circuit is totally powered from a USB (Not connected to the power supply that I am facing issue with. The main problem in my circuit is that, when I use the power supply to act as an input voltage source to my circuit, the circuit seems to draw high current. The control circuit has nothing to do with the power supply.
 

Thanks for clarifying. Regarding excessive quiescent current of charge pump only, you need to check the gate voltage waveforms. I guess you have partly overlapping clocks.

I would expect an input current in the 100 µA range with BSS816, 0.5V Vin and 5V clocks.
 

True.

But I am not happy with your dead times. The flip-flops are usually very fast (rise and fall times) and the mosfets are really not that fast. The capacitors you use slow down the rise and fall times and the square pulses become trapezoidal. Because the graph is symmetric, fall part of one will intersect with the rise part of another around the middle (roughly speaking). That is the part I do not like.
 
ok, I will modify the oscillator circuit as you suggested to increase the dead time period, it seems to be the problem based on your input.

Thanks all for your nice and helpful comments, I really appreciate it.
 

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