Multisource Error during VHDL Synthesis

[sgil]

signal **** has a multi source. vhdl error

Hello all,

I am trying to implement the following code:

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fir_cu is

Port ( fa : in STD_LOGIC;
fb : in STD_LOGIC;
fc : in STD_LOGIC;
f_d : in STD_LOGIC;
clk : in STD_LOGIC;
reset_n : in STD_LOGIC);
-- Y : out STD_LOGIC_VECTOR (3 downto 0); --try to remove unused output ports..
-- fy : out STD_LOGIC;
-- Busy : out STD_LOGIC);
end fir_cu;

architecture Behavioral of fir_cu is

component icon
port
(
control0 : out std_logic_vector(35 downto 0)
);
end component;

component ila
port
(
control : in std_logic_vector(35 downto 0);
clk : in std_logic;
data : in std_logic_vector(53 downto 0);
trig0 : in std_logic_vector(7 downto 0)
);
end component;

signal control0 : std_logic_vector(35 downto 0);
signal ila_data : std_logic_vector(53 downto 0);
signal trig0 : std_logic_vector(7 downto 0);
--
signal cnt : std_logic_vector (7 downto 0);
signal Lstrobe_R1 : std_logic;
signal Lstrobe_R4 : std_logic;
signal Rstrobe_R1 : std_logic;
signal Rstrobe_R4 : std_logic;
signal selR4 : std_logic_vector(1 downto 0);
signal selR1 : std_logic;
signal desel_R1 : std_logic;
signal desel_R4 : std_logic;
signal enable_R1 : std_logic;
signal enable_R4 : std_logic;
signal d_strobe_Ah0 : std_logic;
signal d_strobe_Y : std_logic;
signal a_strobe : std_logic;
signal b_strobe : std_logic;
signal c_strobe : std_logic;
signal d_strobe : std_logic;

signal dummy_busy : std_logic;

begin

i_icon : icon
port map
(
control0 => control0
);

i_ila : ila
port map
(
control => control0,
clk => clk,
data => ila_data,
trig0 => trig0
);

-- Time Slot 0
T0: process(clk)
begin
if(clk'event and clk='1') then
if (fa= '1' and fb = '1' and fc = '1' and f_d = '1') then
if (reset_n = '1') then
cnt <= "00000000";
end if;
end if;

a_strobe <= '1';
b_strobe <= '1';
c_strobe <= '1';
d_strobe <= '1';
selR4 <= "00";
cnt <= cnt + '1';

end if;
end process T0;

-- Time Slot 1
T1: process(clk)
begin
if(clk'event and clk='1') then
if (cnt = "00000001") then
dummy_busy <= '1';
Lstrobe_R1 <= '1';
Lstrobe_R4 <= '1';
cnt <= cnt + '1';

elsif (cnt = "000000010") then
enable_R4 <= '1';
selR4 <= "01";
selR1 <= '0';
desel_R4 <= '0';
cnt <= cnt + '1';


elsif (cnt = "00000011") then
cnt <= cnt + '1';
Lstrobe_R1 <= '0';
Lstrobe_R4 <= '0';
enable_R4 <= '0';

elsif (cnt = "00000100") then
Rstrobe_R4 <= '1';
cnt <= cnt + '1';

elsif (cnt = "00000101") then
d_strobe_Ah0 <= '1';
cnt <= cnt + '1';

elsif (cnt = "00000110") then
cnt <= cnt + '1';
end if;

end if;
end process T1;

-- Time Slot 2
T2: process(clk)
begin
if(clk'event and clk='1') then
if (cnt = "00000111") then
Lstrobe_R1 <= '1';
Lstrobe_R4 <= '1';
cnt <= cnt + '1';

elsif (cnt = "00001000") then
enable_R1 <= '1';
enable_R4 <= '1';
selR4 <= "10";
selR1 <= '1';
desel_R4 <= '1';
desel_R1 <= '0';
cnt <= cnt + '1';

elsif (cnt = "00001001") then
cnt <= cnt + '1';
Lstrobe_R1 <= '0';
Lstrobe_R4 <= '0';
enable_R4 <= '0';
enable_R1 <= '0';

elsif (cnt = "00001010") then
Rstrobe_R4 <= '1';
Rstrobe_R1 <= '1';
cnt <= cnt + '1';
end if;

end if;
end process T2;

ila_data(7 downto 0) <= cnt(7 downto 0);
ila_data(8) <= fa;
ila_data(9) <= fb;
ila_data(10) <= fc;
ila_data(11) <= f_d;
ila_data(12) <= clk;
ila_data(13) <= Lstrobe_R1;
ila_data(14) <= Lstrobe_R4;
ila_data(15) <= Rstrobe_R1;
ila_data(16) <= Rstrobe_R4;
ila_data(18 downto 17) <= selR4(1 downto 0);
ila_data(19) <= desel_R1;
ila_data(20) <= desel_R4;
ila_data(21) <= enable_R1;
ila_data(22) <= enable_R4;
ila_data(23) <= d_strobe_Ah0;
ila_data(24) <= d_strobe_Y;
ila_data(25) <= dummy_busy;

trig0(0) <= fa;
trig0(1) <= fb;
trig0(2) <= fc;
trig0(3) <= f_d;

end Behavioral;

------------------------------------
But i get multiple errors - I checked the Xilinx support website to find possible causes but that didn't really help..or I probably don't know what to change exactly... I get the following:
========================================================================

ERROR:Xst:528 - Multi-source in Unit <fir_cu> on signal <desel_R4>
Sources are:
Signal <desel_R4> in Unit <fir_cu> is assigned to VCC

ERROR:Xst:528 - Multi-source in Unit <fir_cu> on signal <Lstrobe_R1>
Sources are:
Output signal of FD instance <Lstrobe_R1>
Output signal of FDSE instance <Lstrobe_R1_ren>

ERROR:Xst:528 - Multi-source in Unit <fir_cu> on signal <enable_R1>
Sources are:
Output signal of FD instance <enable_R1>
Output signal of FDE instance <enable_R4>

ERROR:Xst:528 - Multi-source in Unit <fir_cu> on signal <selR4<1>>
Sources are:
Signal <selR4<1>> in Unit <fir_cu> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <fir_cu> on signal <selR4<0>>
Sources are:
Signal <selR4<0>> in Unit <fir_cu> is assigned to VCC

ERROR:Xst:528 - Multi-source in Unit <fir_cu> on signal <cnt<3>>
Sources are:
FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.17 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. For more information on this error, please consult the Answers Database or open a WebCase with this project attached at https://www.xilinx.com/support.

Process "Synthesize" failed

 

[ring0]

vhdl error:xst:528 - multi-source

Only one process can be a driver for a signal. In your code there are many signals driven by multiple processes, hence the errors.

 

[sgil]

multi-source in unit xilinx error

Thank you for the prompt reply ring0 ...

You are right...I have one question, when can i have multiple processes? is it only when all the signals being driven in these processes are mutually exclusive/have nothing to do with each other?

In that case, I will modify my code such that I have only one process and see if it works..

 

[ring0]

xilinx fde instance

For example, you can have multiple processes when one process use output from other process. It is only necessary to ensure that no signal is driven by several processes (or parallel assignments).

 

[sgil]

vhdl multi source

I got rid of the errors by using one process and the simulation works perfectly.

Now if i want to use another process that uses the output of the first process does my second process require all those signals (used from process 1) in its sensitivity list? or should 'clk' suffice?

Thanks

 

[ring0]

vhdl error xst 528

For edge-synchronous processes (flip-flops), a clock signal is sufficient for the sensivity list (and asynchronous clear signal if you use it). For latches and asynchronous processes you should mention every signal used in the process in the sensivity list in order to ensure equivalence between simulation and synthesis.