Multiplication using vhdl

[Antros48]

Hi
I am having a problem with my vhdl code made for a multiplication of binary numbers. It keeps showing errors that i do not understand. Is there anyone that could give me a hand, so i upload the program?
Thank you!

 

[Chops211]

What kind of errors are you getting? I need more information in order to help you. Is your design properly reset? How are you multiplying? It would help a great deal if you posted your code.

Thanks

 

[Chops211]

Posting your code so others can see before I answer. Your code is as follows:

--create of multiplier 4bit X 3bit
library ieee;
use ieee.std_logic_1164.all;
--declaratio of the multiplier entity
entity multiplier4X3 is
port ( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (2 downto 0);
P : out std_logic_vector (6 downto 0)
);
end multiplier4X3;

architecture structure of multiplier4X3 is
--call of the 1Bit full adder
--component fulladder1 port(
--a,b,c: in std_logic;
--S,Co: out std_logic);
--end component;
--call of the 4Bit full adder
component fulladder4 port(
x: in std_logic_vector (3 downto 0);
y: in std_logic_vector (3 downto 0);
z: out std_logic_vector (3 downto 0);
Cout : out std_logic );
end component;
--call of the andgate component
component andgate
port (A,B: in std_logic;
D: out std_logic);
end component;

--set the middle signals to use for in-out
signal k,l,m,n,ztemp : std_logic_vector (3 downto 0);
signal Cout1: std_logic;

begin
--ztemp(3 downto 0) <= z (3 downto 0) ;

--the signals for the 12 AND gates
g1: andgate port map (A => A(0), B => B(0),D=> P(0));
g2: andgate port map (A => A(1), B => B(0),D => k(0));
g3: andgate port map (A => A(2), B => B(0),D => k(1));
g4: andgate port map (A => A(3), B => B(0),D => k(2));
g5: andgate port map (A => A(0), B => B(1),D => l(0));
g6: andgate port map (A => A(1), B => B(1),D => l(1));
g7: andgate port map (A => A(2), B => B(1),D => l(2));
g8: andgate port map (A => A(3), B => B(1),D => l(3));
g9: andgate port map (A => A(0), B => B(2),D => m(0));
g10: andgate port map (A => A(1),B => B(2),D => m(1));
g11: andgate port map (A => A(2), B => B(2),D => m(2));
g12: andgate port map (A => A(3), B => B(2),D => m(3));

--one of the middle signals must be set to GND
k(3)<='0';

--declaration for the procedure needed to use the two 4-bit full adder components
stage0: fulladder4 port map (x(3 downto 0)=>k(3 downto 0), y(3 downto 0)=> l(3 downto 0),ztemp(3 downto 0)=>(z(3 downto 1)=>n(3 downto 1), z(0)=>P(1)), Cout=>Cout1);
--stage1: fulladder4 port map (x(1)=>k(1), y(1)=> l(1),z(1)=> n(1));
--stage2: fulladder4 port map (x(2)=>k(2), y(2)=> l(2),z(2)=> n(2));
--stage3: fulladder4 port map (x(3)=>k(3), y(3)=> l(3),z(3)=> n(3),Cout=>Cout1);


--stage4: fulladder4 port map (x(0)=>n(1), y(0)=> m(0),z(0)=> P(2));
--stage5: fulladder4 port map (x(1)=>n(2), y(1)=> m(1),z(1)=> P(3));
--stage6: fulladder4 port map (x(2)=>n(3), y(2)=> m(2),z(2)=> P(4));
--stage7: fulladder4 port map (x(3)=>Cout1, y(3)=> m(3),z(3)=> P(5), Cout=>P(6));
--( 3 => n(3), 2 => n(2), 1 => n(1), 0 => P(1) )
end structure;

---------- Post added at 20:35 ---------- Previous post was at 20:32 ----------

The first problem I see is that the signal z used in this line:

--ztemp(3 downto 0) <= z (3 downto 0) ;

Is not declared anywhere. You must declare signals that are port mapped to your components. From the logic you are using it seems that you use the "n" signal as the z output from the full adders. So change the line to:

ztemp <= n; You don't actually eed the 3 downto 0 since both signals are of the same length and endianness.

Let me know if there are any other problems

 

[Antros48]

Do you mind deleting the code and post only the part that you want to explain???
There are my personal details written on top of it..
Thank you about the response..!

 

[Chops211]

Do you mind deleting the code and post only the part that you want to explain???
There are my personal details written on top of it..
Thank you about the response..!

Deleted your info... You might want to remove the txt!!!

 

[Antros48]

Thank you very much! I will give it a try and let you know about it..

---------- Post added at 22:22 ---------- Previous post was at 21:45 ----------

The z parameter is the one of the 4bit adder above. So it is already declared..well at least this is how i understand it.. But i declared it again as a signal
signal k,l,m,n,ztemp,z : std_logic_vector (3 downto 0); and removed the comment marks on line ztemp(3 downto 0) <= z (3 downto 0) ;.
The error i get is Error (10348): VHDL type mismatch error at multiplier4X3.vhd(57): type of formal parameter "ztemp" does not match port type of value. What im i still doing wrong??

---------- Post added at 22:23 ---------- Previous post was at 22:22 ----------

The z parameter is the one of the 4bit adder above. So it is already declared..well at least this is how i understand it.. But i declared it again as a signal
signal k,l,m,n,ztemp,z : std_logic_vector (3 downto 0); and removed the comment marks on line ztemp(3 downto 0) <= z (3 downto 0) ;.
The error i get is Error (10348): VHDL type mismatch error at multiplier4X3.vhd(57): type of formal parameter "ztemp" does not match port type of value. What im i still doing wrong??

 

[Chops211]

stage0: fulladder4 port map (x(3 downto 0)=>k(3 downto 0), y(3 downto 0)=> l(3 downto 0),ztemp(3 downto 0)=>(z(3 downto 1)=>n(3 downto 1), z(0)=>P(1)), Cout=>Cout1);

This is wrong because in the full adder:

z: out std_logic_vector (3 downto 0);

so instead use:

stage0: fulladder4 port map (
x =>k,
y => l,
z=>ztemp,
Cout=>Cout1
);

The signals between the stages all must be declared in the top level design!!! So now you can use the output ztemp as the input for the next stage. Also, writing it like this is easier to read. And instead of k, l, etc use x0, y0, so you know what stage the signal is in. Just my two cents...:razz:

 

[Antros48]

Ok and for the second part with use of the second full adder i write stage1: fulladder4 port map (x =>n,y => m,z=>P(5 downto 2),Cout=>P(6));
Correct??

 

[Chops211]

Exactly! The input must be the same length as what you describe the component to be. The synthesizer will throw an error if a 2 bit std_logic_vector is sent into an input that expects 3 bits.

Good luck and let me know if you run into any other problems!!!

 

[Antros48]

Well i still get the wrong results on my waveform.. I just want to declare more specific values to signal z.. which are for z(3 downto 1)=>n(3 downto 1), z(0)=>P(1). I mean they all come 4 bits the last three parts of z are equal with n and the fourth with P.. How can i do that? You see the output of the first full adder must be specific so i can add the signals i want to the second one

 

[Chops211]

Temporary signals are your best friend.

simply use another
signal temp : std_logic_vector( 3 downto 0 );

temp <= n( 3 downto 1 ) & P( 1 );

The & signal concats signals together.

 

[Antros48]

so i change my previous statement ztemp(3 downto 0) <= z (3 downto 0) ; by replacing ztemp with temp?? Iam not sure i got it where i can use this signal..

 

[Chops211]

If you are taking an output from stage0 and you want to manipulate it in some way before you feed it to stage1, then you can take the signal z( 3 downto 0 ) and use it with an intermediate signal to produce the input for the next stage.

Say you are using the statement ztemp(3 downto 0) <= z (3 downto 0). According to your example, you want to use the 3 MSB of z and concat with the signal P( 1 ). In order to do this, you can create an intermediate signal called anything (use temp for example) and do the following:

temp <= z( 3 downto 1 ) & P( 1 );

And now use temp as the input to the next stage or wherever it needs to be routed to.

 

[Antros48]

Error (10309): VHDL Interface Declaration error in multiplier4X3.vhd(54): interface object "P" of mode out cannot be read. Change object mode to buffer.
Do i have to declare another variable for P in my begin part??

 

[Chops211]

I didn't see that P is an output in your top level design. You need to declare a signal that can be used internally that you would then set P equal to. You cannot read an output signal.

It seems like this is the first time you worked with structural VHDL design. I suggest you read: VHDL Tutorial

It will clear up a lot of the issues you are having.

 

[Antros48]

Something like Ptemp<=P(1);? But then it should be like reading the output.

 

[Chops211]

All places where you use z( x ) => P( x ), change P to Ptemp and at the bottom of the add:
P <= Ptemp;

 

[Antros48]

I will give it a try! Thanks!

---------- Post added 14-11-11 at 00:19 ---------- Previous post was 13-11-11 at 23:34 ----------

Is there any program for debugging?? Because i wrote the code correct , in my opinion, according to your thoughts and although i have no more errors the simulation file has wrong results e.g. 2*2 = 0.

 

[Chops211]

What are you using to synthesize? Xilinx ISE?

You can use ModelSim to simulate. It's very easy to use and will allow you to debug. There must be some issues with the logic or how some signals are routed. Simulate the entire top level design and make sure each signal is the correct value it should be.

Good luck

 

[shanmugaveld]

"although i have no more errors the simulation file has wrong results e.g. 2*2 = 0."

Wrong results may be because of the bit widths
say your equations is like this "c <= a*b;"
if a and b are declared with two bits,i.e (1 downto 0)
if C is also declared two bits then you may get the above results as you have given.