multiplexer - vhdl - fpga

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Tamas888

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Hello
I have a question:
I have a following code in vhdl:

process
begin
A<=B;
wait 10ns;
A<=C;
wait 10ns;
end
So the sensitivity list is empty and I know the above code will work periodically. In the first 10ns B input will be on A output and the second 10ns C input will be on the A output. But what happen if B changes during the execution for example in the 2ns? will it appear on the output immediately or only after the next period?

Thanks,

Tamas
 

Hi,

when you write the VHDL you cannot insert the delay inside your code because there isn't a time variable.
This seems a test bench that is used to simulate the behaviour of the code and it has nothing to do with mux as you write in the title.

Daniel
 
This is definitely not a MUX design.. however to answer your question, if B changes after 2 ns of the delay it will still not be updated at the output as the process is waiting for 10ns and it will not execute anything during this wait period..
 
With the code you posted, A will change to the value of B/C at that point in time. changes in B or C have no effect on A until A is next assigned.

This is not a mux, and this is not synthesisable code.
 
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