Multiplexer using D flip flops

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shikharmakkar

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I want to design a multiplexer using d flip flops and some combinational logic. I tried making the circuit but the output depends on the clock, that is how should I remove the previous state dependency when the clock goes low? Should I first convert it into a d latch and then proceed?
 

Hi,

Multiplexers usually are non clocked.
D-FlipFlops are clocked.

Why do you want to design a multiplexer with D-FlipFlops?

**********

There are many multiplexers, we don´t know wich one you want to design.
So please give more information, schematic and tell waht you expect, and what is not like you expected.

Klaus
 

You can't remove, just accept it.

DFFs are often used for continuously clocked high speed multiplexers to regenerate the signal timing.
 

FvM said:
You can't remove, just accept it.

DFFs are often used for continuously clocked high speed multiplexers to regenerate the signal timing.
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ok, then can you design it? what i did was i made the output logic of a mux as the output and put a clk and in clear signal, i put the complement of the clock so that when it goes low, the previous state is removed but it is still edge triggered
 

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