Multiplex address and data bus in Verilog

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joc_06

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verilog bus

Hi i have 2 8 bit address and data buses and a clock.
I want to put these onto 1 bus using the clock in verilog

Im thinking of something like this:

Code: 
always @ posedge clock
            temp1 = addr;

always @ negedge clock
            temp2 = data;

assign multiplexed_addr_data = temp1 (some operator) temp2;

How can i finalise this? any other suggestions?
I need a solution that is good for synthesis so the clock cant be used in the combinational logic part
Thank you

Added after 11 minutes:

this is the way i was going to do it which is functionally fine but is a disaster for synthesis:

Code: 
always @ clock
    if clock
     mult_addr_data = addr;
    else 
     mult_addr_data = data;
 

verilog buses

What type chip are you using, and what is the clock frequency? It's probably better to double the clock frequency and do everything on the clock's rising edge. Or maybe use DDR flops, if your chip provides them.
 

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    joc_06

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verilog bus syntax

its actually for an asic not an fpga.
If i double the clock rate, how can i multiplex the buses in verilog?
thanks
 

verilog assign bus

You may want to ask your question in the ASIC forum. ASIC techniques are sometimes very different from FPGA. I don't know ASIC.

After doubling the clock, you will need a control register that toggles to select the desired bus. Something like this simple example:

Code: 
wire [15:0] addr, data;
reg         select = 0;
reg  [15:0] mult_addr_data;

always @ (posedge clk) begin
  select <= ~select;
  mult_addr_data <= select ? addr : data;
end
 

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    joc_06

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what do you mean by multiplexing the bus?

excellent, thank you....

but is that allowable for synthesis using a mux type statement in an always block?
 

what do you mean by multiplexing the bus

Yes. The ? : is called the "conditional" operator. A nice feature borrowed from C.
 

verilog address bus mux

Yes i know this operator but i did not think it should be used in a clocked block as it combinational. it is against our coding guidelines here.

thank you
 

verilog bus

Here I changed the code little bit ...
Code: 
wire [15:0] addr, data;
reg         select = 0;
reg  [15:0] mult_addr_data;
wire [15:0] mult_addr_data_nx;

//assign mult_addr_data_nx = select ? addr : data;

always@(addr or data or select)
   if (select)
     mult_addr_data_nx = addr;
   else
     mult_addr_data_nx = data;
   
always @ (posedge clk) begin
   select <= ~select;
   mult_addr_data <= mult_addr_data_nx;
end
 

bus in verilog

always @ (posedge clk) begin
select <= ~select;
mult_addr_data <= select ? addr : data;
end
Click to expand...

I would like to draw your attention on select signal. You must set it in a predictable state at start-up, else you will not be able to distinguish data from address.

I mean, you should use reset signal:
Code: 
always @ (posedge clk) begin 
  if (reset) select <=0;
     else select <= ~select; 
  mult_addr_data <= select ? addr : data; 
end
 

bus verilog

joc_06, your guidelines don't allow expressions in clocked assignments? How sad! I wonder what is the rationale of such rules?

YUV, the statement reg select = 0; does the initialization. That's the most economical way to do it in an FPGA. ASIC may not allow such initialization, however. Either way no big deal, because the final design will probably use something other than a toggle flop to generate "select".
 

vhdl code for multiplex address and data bus

echo47 said:
the statement reg select = 0; does the initialization.
Click to expand...

I see. But at power up, an external device, that supplies address/data on the bus, may start working earlier than our one. So, some operations might be lost and the state of select will be really unknown.
I think, it would be better to sacrifice one pin to control address/data bus and forget this headache.
 

multiplex address

here is how i've done it:

the on chip portion:
Code: 
// Mux Port A address and Data onto single 8 bit bus
   assign s_addr_temp = s_wena ? address : r_addr_temp;
   assign s_ad = s_wena ? data : r_addr_temp; 

   always @ (posedge clk)
        if (!reset)
          r_addr_temp <= 8'b0;
        else
          r_addr_temp <= s_addr_temp;
here i needed to register the address so i wont lose it.
s_ad is my muxed data bus
i also send the write strobe and clock off chip


the off chip portion: ie decoder logic
Code: 
 // Mux Port A address and Data onto single 8 bit bus
   assign s_d = s_wena ? s_ad : r_d;
   assign s_a = !s_wena ? s_ad : s_a; 

   always @ (posedge clk)
        if (!reset)
          begin
          r_d <= 8'b0;
          end
        else
          begin
          r_d <= s_d;
          end

here i reg data so i wont lose it

s_a is my final address bus and r_d is my final data bus

thank you
what do you think of my solution?

Added after 2 minutes:

It would not be possible for me to use an initialise statement like:
reg select = 0;

this is terrible coding i feel (no offense) and would not be good for an asic or any kind of synthesis
 
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    RaviT

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