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Is there a way to remove the extra cycle each signal is taking after the first output? Seems like Alu_logic output is taking extra cycle, and Load logic and its delay then starts and takes effect. The same way Load_logic is going into region of store_logic, it all continues to branch logic too. 40ns is actually giving delay of 60ns thus, 60ns giving delay of 80ns. Why this extra 20ns each time?