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That was because when I saw statements like "wait until rising_edge(clk);" in your post, I thought you were writing testbench code. So I wanted to tell you about various delays that can be used in VHDL testbench code. But at Post #6 you told me that it was synthesizable code!

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Also pay attention to Post #2 by [USER=152255]@FvM[/USER].

....my bread and butter depends on the quality of VHDL code I write and a newbie is telling me to learn VHDL, OMG!

Sorry that I tried to help an arrogant Newbie. I am definitely out of this thread!