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Its the same, I just added those lines of you with signal checker..Intiially there is extra cycle added as you see in waveform. It is taking an extra cycle instead of just one, to make Alu_logic a 1. You cant simulate it at your end?

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You yourself dont know VHDL, thats why you suggested use of after statement. After statement gives inertial delay, but you think its transport delay. I have already told you after statement doesn't work for this program. You are just wasting time of both of us. Why dont you learn VHDL first, before telling me to learn it??