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Then just put this in the garbage bin (yes I am being this straightforward) and write fresh RTL code in which you have process blocks with sensitivity lists.

You must write synthesizable RTL code and there are rules to write synthesizable RTL code.

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This approach for logic design is also completely wrong!

You must FIRST write RTL code which is synthesizable and then write code for test bench,  which will generate peripheral signals to verify your synthesizable code using behavorial simulation.

Nevertheless follow a good tutorial for RTL design and learn the basics first!