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This is program code, not the testbench. I was using after previously as you mentioned but second after nullifies first one for each of if else above. Wait actually is doing something at least, but output is not right one. I think its not possible to simulate it in this way in VHDL, at least by using the transport, after and wait given in language itself.

[QUOTE="arifboy, post: 1790637, member: 695315"] This is program code, not the testbench. I was using after previously as you mentioned but second after nullifies first one for each of if else above. Wait actually is doing something at least, but output is not right one. I think its not possible to simulate it in this way in VHDL, at least by using the transport, after and wait given in language itself. [/QUOTE]

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