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Shows that this is a testbench use case!

You can use "wait" statements to wait for a specific amount of time.

To delay a signal before assigning it to some other signal at the testbench, you can use transport dealy modeling (e.g. sig2 <= sig1 after 7 ns).

But since it seems you are writing a test bench for some sequential logic (cpu, etc...). So I would highly advise you to write a testbench containing process statements which has the clock in the sensitivity list. You will have a lot of control and clear understanding of what is being done.  I do not support the way you have written the TB to simulate your DUT.

Additionally - the advice given in the post above!