Multiple ring oscilators verilog code

wire [5:0] node;
assign node = {~node[4:0], ~node[5] & en};

always @(*) begin
  node <= #10 {~node[4:0], ~node[5] & en};
end

[syntax=verilog]
module tryring_tb;

reg en;
wire osc_out;
//input en;
//output osc_out;



initial begin
en = 1'b0;
#5 en = 1'b1;
end

tryring  u_tryring( .en(en), .osc_out(osc_out));

endmodule

module tryring (en, osc_out);
input en;
output osc_out;
wire osc_out_reg;

reg [4:0] node /* synthesis keep*/ ;
assign node=5'b11111;

reg osc_out_reg;


//always @(en or osc_out_reg)
always @(*)

begin
node[0]<= ~(node[4] & en);
node[1]<= ~node[0]; 
node[2]<= ~node[1];
node[3]<= ~node[2];
node[4]<= ~node[3];


osc_out_reg<=node[4];

end 

assign osc_out= osc_out_reg;
 
endmodule 


assign wire0 = ~ wire1;
assign wire1 = ~ wire2;


[/syntax]

[syntax=verilog]
module top (in, sel, osc_out);

input [7:0] in;
input [2:0] sel;
wire [3:0] en;

//output [99:0] osc_out ;

output [3:0] osc_out ;

//generic_RO u_generic_RO1(.osc_out(osc_out[24:0]), .en(en[0]));
//generic_RO u_generic_RO2(.osc_out(osc_out[49:25]), .en(en[1]));
//generic_RO u_generic_RO3(.osc_out(osc_out[74:50]), .en(en[2]));
//generic_RO u_generic_RO4(.osc_out(osc_out[99:75]), .en(en[3]));

generic_RO u_generic_RO1( .en_G(en[0]), .osc_out_G(osc_out[0]));
generic_RO u_generic_RO2( .en_G(en[1]), .osc_out_G(osc_out[1]));
generic_RO u_generic_RO3( .en_G(en[2]), .osc_out_G(osc_out[2]));
generic_RO u_generic_RO4( .en_G(en[3]), .osc_out_G(osc_out[3]));


mux_top u_mux_top(.in (in),.sel (sel), .en_out (en) );
						 			
									
endmodule								

module mux_top(in,sel, en_out);

input [7:0] in;
input [2:0]  sel;
output [3:0] en_out;

reg [3:0] en_out;

always @ (sel or in)
begin 
 case(sel) 
    3'b000 : begin 
	 en_out[0] = in[0];
    				 en_out[3:1] = 3'b0;
					 end
    3'b001 : begin
				 en_out[0] = in[1];
             en_out[3:1] = 3'b0;
				 end
     3'b010 : begin
	              en_out[1] = in[2];
     				  en_out[3:2] = 2'b0;
     				  en_out[0] = 1'b0;
					  end
      3'b011 : begin
		en_out [1] = in[3];
     					 en_out[3:2] = 2'b0;
     				   en_out[0] = 1'b0;
     				   end
       3'b100 : begin
		 en_out[2] = in[4];
      					en_out[3] = 1'b0;
     				   	en_out[1:0] = 2'b0;
							end
        3'b101 : begin
		  en_out[2] = in[5];
        				en_out[3] = 1'b0;
     				   		en_out[1:0] = 2'b0;
								end
         3'b110 : begin
			en_out[3] =in[6];
         				  en_out[2:0] = 3'b0;
     				   		end
          3'b111 : begin
			 en_out[3] = in[7];
          				 en_out[2:0] = 3'b0;
 end
 endcase 
end

endmodule

module generic_RO (en_G, osc_out_G);

input en_G;
output osc_out_G;

reg [num-1:0] RO_out_arr;


parameter num=25;

//reg RO_out_AND = 1'b1;
                                                                                                                        
genvar i;//,j;    
generate
	                                                                                                              
		//for (j=0; j<4; j=j+1) begin :inst1
			for(i=0; i<num; i=i+1) begin :inst
				
				
								ringosc5 ringosc_n(
								                   .Rosc_out  (RO_out_arr[i]),
														 
								                   .en       (en_G)  
														 );                                                                                           
																				
							//	RO_out_AND = (RO_out_arr[i] && RO_out_AND); //j variable will be constant for i=1 to 25. 
																					 //After 25 times of i, j increments 1 time.
									
			
	//end
				end  
	                                                                                                                          
//assign osc_out_G = RO_out_AND;
endgenerate     

endmodule

module ringosc5 (Rosc_out, en);
input en;
output Rosc_out;
wire  Rosc_out;
reg [5:1] node /* synthesis keep*/;
reg Rosc_out_reg;


always @(Rosc_out or en)
begin
node[1]<= ~(node[5] & en); 
node[2]<= ~node[1];
node[3]<= ~node[2];
node[4]<= ~node[3];
node[5]<= ~node[4];

Rosc_out_reg<=node[5];

end 

assign Rosc_out = Rosc_out_reg;
 
endmodule