nitint08
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I have few doubts on reset-polarity. Please share your thoughts.
1. Can there be multiple polarities of reset feasible in a design?
2. If Flop (F1) output is reaching another Flop (F2) via a inverter, will such situation be consider as design with multiple reset-polarity.
assuming reset as active high, on reset, flop is cleared (Q=0). Since the output is fed to another Flop reset which also
also get cleared.
But in normal operation, Data is moved ahead and when F2 clear pin gets 1, it clears the Flop.
1. Can there be multiple polarities of reset feasible in a design?
2. If Flop (F1) output is reaching another Flop (F2) via a inverter, will such situation be consider as design with multiple reset-polarity.
assuming reset as active high, on reset, flop is cleared (Q=0). Since the output is fed to another Flop reset which also
also get cleared.
But in normal operation, Data is moved ahead and when F2 clear pin gets 1, it clears the Flop.