Multiple processes in vhdl..

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Deepika.R

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How are multiple processes executed in vhdl.. Deos it happen concurrently..??
 

As you know VHDL is a HDL language and HDL languages are executed concurrently. But there is a feature in HDLs that allows you to write your code like
traditional languages(C, Java, ...) and that is "process" keyword in VHDL. Also processes are executed concurrently. In fact compiler counts them as two
separated hardware modules that each one makes some of your outputs.
 


I would NOT compare HDL languages to C, and especially not processes. Inside a process you can assign signals or variables, and each behave differently (which is vary much unlike C). Gettting these mixed up can lead to all sorts of problems.
 
Deepika.R said:
How are multiple processes executed in vhdl.. Deos it happen concurrently..??
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In HDL language, if you want to make any logic sequential, you should design it. Assignments are always concurrent. Output appears after some transport delay. You can have n number of process, but all statements inside each process still will execute at the same instant of time. Dont compare it with C, it is way too different.
 
I would NOT compare HDL languages to C, and especially not processes. Inside a process you can assign signals or variables, and each behave differently (which is vary much unlike C). Gettting these mixed up can lead to all sorts of problems.
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Dear TrickyDicky,
I surely didn't/don't/wont compare HDL languages and C. I just meant inside processes, instructions are executed sequentially like C.
 

moottii said:
Dear TrickyDicky,
I surely didn't/don't/wont compare HDL languages and C. I just meant inside processes, instructions are executed sequentially like C.
Click to expand...

Yes they are, and no they are not.
They will be, but signals will only take the last assignment given to them, ignoring any previous assignments.

It will also be confusing, because of the way signals are updated, so if you did this code:

Code: 
signal a : integer := 5;
signal b : integer := 10;

process(clk)
begin
  if rising_edge(clk);
    a <= 0;
    b <= a;
  end if;
end process;
;

First of all, nothing actually until there is a rising edge of the clock. Secondly, on the first clock edge b will be assigned the value 5, not 0, even though the assignment to a was put before B, because of the way signals work. So comparing it to C can cause a misunderstanding.
 

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