Sep 25, 2011 #1 S sijukrishnan Member level 1 Joined Jul 11, 2011 Messages 33 Helped 4 Reputation 8 Reaction score 4 Trophy points 1,288 Location India Activity points 1,479 Hi all, Let me make a general query related to PCIe. Consider there is a 8-lane PCIe root complex integrated in a SoC. Can I connect the root complex to eight independent single lane PCIe end points? If yes, how the reference clock to be routed? How should be the architecture. Thanks Siju
Hi all, Let me make a general query related to PCIe. Consider there is a 8-lane PCIe root complex integrated in a SoC. Can I connect the root complex to eight independent single lane PCIe end points? If yes, how the reference clock to be routed? How should be the architecture. Thanks Siju