multiple PCIe end-points in single root complex?

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sijukrishnan

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Hi all,


Let me make a general query related to PCIe.



Consider there is a 8-lane PCIe root complex integrated in a SoC. Can I connect the root complex to eight independent single lane PCIe end points? If yes, how the reference clock to be routed? How should be the architecture.



Thanks

Siju
 

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