multiple packed dimensions are not allowed in this mode of verilog

[aditik19]

// Define Sobel operator kernels
localparam [2:0][2:0] x_kernel ={ "-1, 0, 1", "-2, 0, 2", "-1, 0, 1" };
localparam [2:0][2:0] y_kernel = { " -1, -2, -1 ", " 0, 0, 0 ", " 1, 2, 1 "};

i am getting error

multiple packed dimensions are not allowed in this mode of verilog.

i want to implement it on vivado zcu106 board for edge detection for image processing and add hdmi to it

thank you

 

[std_match]

// Define Sobel operator kernels
localparam [2:0][2:0] x_kernel ={ "-1, 0, 1", "-2, 0, 2", "-1, 0, 1" };
localparam [2:0][2:0] y_kernel = { " -1, -2, -1 ", " 0, 0, 0 ", " 1, 2, 1 "};
i am getting error multiple packed dimensions are not allowed in this mode of verilog.
i want to implement it on vivado zcu106 board for edge detection for image processing and add hdmi to it

thank you

Try something like this:

{ {-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1} };

 

[aditik19]

Try something like this:

{ {-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1} };

• tried this but still getting error like multiple packed dimensions are not allowed in this mode of verilog and concatenation unsized literal: will interpret as 32 bits

 

[FvM]

A regular array spec has the range declaration(s) after the identifier.

 

[aditik19]

A regular array spec has the range declaration(s) after the identifier.

how to declared can you please guide me?
thank you

 

[FvM]

localparam x_kernel [2:0][2:0]

 

[aditik19]

localparam x_kernel [2:0][2:0]

localparam x_kernel [2:0][2:0] ={ {-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1}};
error

• parameter 'x_kernel' with unpacked dimension should have a data type and parameter with unpacked dimensions is only allowed in system verilog

--- Updated Apr 26, 2023 ---

module edge_detection (
input clk,
input rst,
input [7:0] video_in,
output reg [7:0] video_out,
output reg hsync,
output reg vsync
);

// Define constants
localparam H_RES = 1920; // Horizontal resolution
localparam V_RES = 1080; // Vertical resolution
localparam H_FRONT_PORCH = 88; // Front porch of horizontal sync
localparam H_SYNC_WIDTH = 44; // Width of horizontal sync
localparam H_BACK_PORCH = 148; // Back porch of horizontal sync
localparam V_FRONT_PORCH = 4; // Front porch of vertical sync
localparam V_SYNC_WIDTH = 5; // Width of vertical sync
localparam V_BACK_PORCH = 36; // Back porch of vertical sync
localparam THRESHOLD = 128; // Edge detection threshold

// Define state machine states
localparam [2:0] IDLE = 3'b000;
localparam [2:0] ACTIVE = 3'b001;
localparam [2:0] HSYNC = 3'b010;
localparam [2:0] VSYNC = 3'b011;

// Define state machine
reg [2:0] state = IDLE;

// Define horizontal and vertical counters
reg [10:0] h_count = 0;
reg [10:0] v_count = 0;

// Define video buffer
reg [7:0] video_buf[H_RES-1:0][V_RES-1:0];

// Define Sobel operator kernels
localparam [2:0][2:0]x_kernel ={ {-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1}};
localparam [2:0][2:0] y_kernel = { { -1, -2, -1 }, {0, 0, 0 }, {1, 2, 1 }};



// Define Sobel operator buffers
reg signed [15:0] sobel_buf_x[H_RES-3:0][V_RES-3:0];
reg signed [15:0] sobel_buf_y[H_RES-3:0][V_RES-3:0];
reg [7:0] sobel_buf[H_RES-3:0][V_RES-3:0];

// Process video input
always @(posedge clk) begin
if (rst) begin
h_count <= 0;
v_count <= 0;
state <= IDLE;
video_out <= 0;
hsync <= 1;
vsync <= 1;
end else begin
case (state)
IDLE: begin
h_count <= 0;
v_count <= 0;
video_out <= 0;
hsync <= 1;
vsync <= 1;
if (h_count >= H_BACK_PORCH) begin
h_count <= 0;
state <= HSYNC;
end
end
ACTIVE: begin
video_buf[h_count-1][v_count-1] <= video_in;
h_count <= h_count + 1;
if (h_count >= H_RES) begin
h_count <= 0;
v_count <= v_count + 1;
if (v_count >= V_RES) begin
v_count <= 0;
state <= IDLE;
end
end
end

endcase
end
end
endmodule


this is the code foe HDMI ZCU106 edge detection

 

[FvM]

Works for me

localparam integer x_kernel [2:0][2:0] ='{ '{-1, 0, 1}, '{-2, 0, 2}, '{-1, 0, 1}};

Compiler syntax set to system verilog.

 

[aditik19]

Still there is an error

localparam integer x_kernel [2:0][2:0] ={ {-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1}};

• wrong element type in unpacked array concatenation
• multiple packed dimensions are not allowed in this mode of verilog

 

[FvM]

Tried post #8 suggestion?

 

[aditik19]

localparam integer x_kernel[2:0][2:0] = '{ '{-1, 0, 1}, '{-2, 0, 2}, '{-1, 0, 1}};

• Error - Syntax error near "'".
• Warnings - extra semicolon is not allowed here in this dialect. use SV mode

 

[FvM]

Any reason you don't set the compiler to system verilog syntax?

 

[aditik19]

i am using vivado

 

[aditik19]

module hdmi_sobel (

input clk,

input rst_n,

input [7:0] in_pixel,

output reg [7:0] out_pixel,

output reg [7:0] h_sync,

output reg [7:0] v_sync,

output reg [7:0] de,

output reg [7:0] h_blank,

output reg [7:0] v_blank

);



// Declare the HDMI synchronization signals

reg [10:0] h_counter;

reg [10:0] v_counter;

wire [7:0] sobel_out_pixel;

(* IOSTANDARD = "LVCMOS33" *)// Add this attribute to specify the I/O standard



// Declare the Sobel operator module

//assign out_pixel = sobel_out_pixel;

sobel_operator sobel_inst(

.clk(clk),

.reset(rst_n),

.in_pixel(in_pixel),

.out_pixel(sobel_out_pixel),

.v_blank(v_blank)

);





always @(posedge clk) begin

if (!rst_n) begin

out_pixel <= 0;

end

else begin

out_pixel <= sobel_out_pixel;

end

end





// Horizontal synchronization

always @(posedge clk) begin

if (!rst_n) begin

h_sync <= 1;

h_counter <= 0;

end

else begin

if (h_counter >= 799) begin

h_sync <= 0;

h_counter <= 0;

end

else begin

h_sync <= 1;

h_counter <= h_counter + 1;

end

end

end



// Vertical synchronization

always @(posedge clk) begin

if (!rst_n) begin

v_sync <= 1;

v_counter <= 0;

end

else begin

if (v_counter >= 524) begin

v_sync <= 0;

v_counter <= 0;

end

else if (h_counter >= 799) begin

v_sync <= 1;

v_counter <= v_counter + 1;

end

end

end





// Data enable signal

always @(posedge clk) begin

if (!rst_n) begin

de <= 0;

end

else begin

de <= ~h_blank & ~v_blank;

end

end





// Horizontal blanking

always @(posedge clk) begin

if (!rst_n) begin

h_blank <= 1;

end

else begin

if (h_counter >= 640 && h_counter <= 800) begin

h_blank <= 0;

end

else begin

h_blank <= 1;

end

end

end





// Vertical blanking

always @(posedge clk) begin

if (!rst_n) begin

v_blank <= 1;

end

else begin

if (v_counter >= 490 && v_counter <= 525) begin

v_blank <= 0;

end

else begin

v_blank <= 1;

end

end

end

endmodule



// HDMI module with Sobel operator



module sobel_operator (

input clk,

input reset,

input [7:0] in_pixel,

output reg [7:0] out_pixel,

input [7:0] v_blank

);



// sobel_operator code here

endmodule

• I have added this it synthesis the code but getting error in implementation part like Black Box Instances: Cell 'sobel_inst' of type 'sobel_operator' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
• Error(s) found during DRC. Opt_design not run.
• please help me to solve the error

 

[dpaul]

i am using vivado

The Vivado simulator supports a subset of SystemVerilog required by synthesis.

You have not answered why you do not use the SV switch during compilation!

 

[aditik19]

The Vivado simulator supports a subset of SystemVerilog required by synthesis.

You have not answered why you do not use the SV switch during compilation!

hi,
I think the design may not need any compile-time switches to function correctly
that's why but you can suggest me and please let me know which i need to improve and add the part in my design

Thank you

Best Regards

 

[dpaul]

I do not have your project environment so I cannot tell what you are doing wrong unless you specifically show them here.

Cell 'sobel_inst' of type 'sobel_operator' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

I can only guess, make sure the sub-module sobel_operator is added to your project.

 

[aditik19]

I do not have your project environment so I cannot tell what you are doing wrong unless you specifically show them here.

I can only guess, make sure the sub-module sobel_operator is added to your project.

yes i have added it and it showing error
module sobel_operator (
input clk,
input reset,
input [7:0] in_pixel,
output reg [7:0] out_pixel,
input [7:0] v_blank
);
(* IOSTANDARD = "LVCMOS33" *) // Add this attribute to specify the I/O standard

reg signed [7:0] h_kernel [0:2];
reg signed [7:0] v_kernel [0:2]; // Vertical Sobel kernel coefficients
reg signed [17:0] h_sum, v_sum; // Intermediate sum variables for horizontal and vertical filtering
reg signed [17:0] g_mag; // Gradient magnitude
reg signed [8:0] g_angle; // Gradient angle (in degrees)
parameter real pi = 3.14159;
// Initialize Sobel kernels



// reg [7:0] h_kernel [2:0]; // 2-dimensional memory with 8-bit values

always @* begin
h_kernel[0][0] = 1;
h_kernel[0][1] = 2;
h_kernel[0][2] = 1;
h_kernel[1][0] = 0;
h_kernel[1][1] = 0;
h_kernel[1][2] = 0;
h_kernel[2][0] = -1;
h_kernel[2][1] = -2;
h_kernel[2][2] = -1;
end

// Horizontal Sobel filter
always @(*) begin : sobel_always
integer i;
integer j;
h_sum = 0;
for (i=-1; i<=1; i=i+1)
begin
for (j=-1; j<=1; j=j+1)
begin
h_sum = h_sum + h_kernel[i+1][j+1] * in_pixel[8*(i+1)+(j+1)];
end
end
end

// Vertical Sobel filter
always @(*) begin : sobel1_always
integer i;
integer j;
v_sum = 0;

for (i=-1; i<=1; i=i+1) begin
for (j=-1; j<=1; j=j+1) begin
v_sum = v_sum + v_kernel[i+1][j+1] * in_pixel[8*(i+1)+(j+1)];
end
end
end

// Compute gradient magnitude and angle


always @(*) begin
g_mag = $signed(h_sum + v_sum);
if (h_sum == 0) begin
if (v_sum > 0) g_angle = 90;
else if (v_sum < 0) g_angle = 270;
else g_angle = 0;
end
else begin
g_angle = $signed((180/$pi)*atan(v_sum/h_sum));
if (h_sum < 0) g_angle = g_angle + 180;
if (g_angle < 0) g_angle = g_angle + 360;
end
end




// Output the gradient magnitude
always @(posedge clk) begin
if (!reset && v_blank) begin
out_pixel <= { 8{g_mag[8]} }; // Output only the most significant bit of the magnitude
end else begin
out_pixel <= 8'h00;
end
end

endmodule