In a big schematic design, there are several net labels connected to the same node.
When I upload sch to pcb, one is selected arbitrarily. Therefore I may see 'ENABLE_XXYY' label on traces/vias/pads etc. instead of 'GND' for my global gnd.
In Altium, every net should have a unique net label, otherwise such conflicts might arise. You will be warned about this when you compile your schematic design though. A notable exception are nets connected to Power Ports, they automatically get the same name as their respective Ports.
Assigning a unique net name for all the traces ultimately getting together is of course a logical way.
If I connect two net names to each other, altium selects one of them as a common net name. The question is: How can I select it? Not Altium. In hierarchical designs, it is inevitable.