Multiple interleave winding and leakage inductance?

[treez]

This time we have a full bridge traxformer to wind
Its a single primary coil, and a centre tapped secondary


We can either do...

1...PRI / SEC / PRI / SEC / PRI

or

2..PRI / SEC SEC / PRI

do you know which gives less leakage inductance.

 

[Warpspeed]

Number one.

Only disadvantage is that with more layers to insulate, the extra insulation will consume valuable space that would be better filled with copper.

 

[Velkarn]

i agree, number one.
also interleaved winding better eliminate proximity effect.
but one more disadvantage - the capacitance of transformer increases and emi level will be higher

 

[FvM]

Center tapped secondary means that you asking for leakage inductance between primary and each secondary windings halve?

If "SEC" in the diagram actually represents a half winding, case 2 is probably better.

To estimate the leakage inductance of various interleaved windings configurations, refer to Snelling Soft Ferrites, section properties of windings.

 

[treez]

Thanks FvM

Pg 356 of the text you kindly reference.. “soft ferrites….” By Snelling confirms that the number of layers does indeed dramatically reduce leakage inductance, as it goes by a square law.

Though obviously of there are too many sections, then there will be too many turns, and the N^2 term will start denigrating it.

The equation on that page presumably refers to those separate coil sections being in series…..some may think that those different sections are just parallel sections

- - - Updated - - -

also interleaved winding better eliminate proximity effect.
but one more disadvantage - the capacitance of transformer increases and emi level will be higher

..Thanks Velkarn, I see what you mean, but those layers would be there anyway, so its not as if there are more layers, so the capacitance will be the same?, I mean, interleaving different windings presumably doesn't increase capacitance..or does it?..woops , I suppose it must increase inTERwinding capacitance, whilst reducing inTRAwinding capacitance?

 

[FvM]

There's no difference between series and parallel circuit if the coupling factors of individual windings are equal.

In an asymmetrical geometry, the parallel configuration can be expected to give slightly better overall coupling. But the difference can be probably ignored for a first oder estimation.

 

[treez]

if the interleaving sections can just be paralleled bits then that means paralleling is giving lower leakage, because with parallel sections, the "lw" term will be less?

I always thought that the interleave sections had to be in series with each other. oh well.

 

[Velkarn]

..Thanks Velkarn, I see what you mean, but those layers would be there anyway, so its not as if there are more layers, so the capacitance will be the same?, I mean, interleaving different windings presumably doesn't increase capacitance..or does it?..woops , I suppose it must increase inTERwinding capacitance, whilst reducing inTRAwinding capacitance?

between layers and interleaved layers there is a diference. with interleaved layers the area is more, so the capacitance increases, i think. i had an experience - we maked transformer with interleaving PSPSP, converter with this transformer did not pass the EMI test. and than we had to remake transformer soS. and emi level becomes lower
besides, in some PI ref designs i saw shield windings in transformers with interleaving.

 

[Orson Cart]

shield layers are a good idea for multiple interleaved windings to reduce RFI on the i/p's and o/p's....