Multiple instantiation of a MUX

streetHawkk said:

Hi Friends,

Please guide me if my approach is not correct. Basically i have requirement where i need to use a MUX to access a shared memory from 4 different modules.
I have a multiplexer module with four possible selections as shown below.

MUX_AD
------
S1:S0 = "00", "01", "10" & "11"

---

Code VHDL - [expand]
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entity MUX_AD is
(
* addra : IN std_logic_vector(4 downto 0);
* douta : OUT std_logic_vector(7 downto 0);
* sel   : IN std_logic_vector(1 downto 0)
);
end entity;

---

I have 4 components say A, B, C & D which requires to use this mux to access this memory.

Can i instantiate the MUX_AD in each of these different components and connect accordingly. Will this work.


Component A : selects S1:S0 = "00"
Component B : selects S1:S0 = "01"
Component C : selects S1:S0 = "10"
Component D : selects S1:S0 = "11"

---

Code VHDL - [expand]
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========================
Component A (compA.vhdl)
-----------
 
signal compA_addra : std_logic_vector(4 downto 0);
signal compA_douta : std_logic_vector(7 downto 0);
signal compA_sel: std_logic_vector(1 downto 0);
 
Port mapping
------
  ap : MUX_AD PORT MAP(
    addra => compA_addra,
    douta => compA_douta,
    sel   => compA_sel
  )
 
========================
Component B  (compB.vhdl)
-----------
 
signal compB_addra : std_logic_vector(4 downto 0);
signal compB_douta : std_logic_vector(7 downto 0);
signal compB_sel: std_logic_vector(1 downto 0);
 
Port mapping
------
  ap : MUX_AD PORT MAP(
    addra => compB_addra,
    douta => compB_douta,
    sel   => compB_sel
  )

---

Similary for other 2 components C & D from separate vhdl files.

Thanks
Hwk

Click to expand...