Kenny0820
Newbie
Hi all, I encountered a weird problem, shown in figure below, why does my VCD file have two states in a timing #200000 for a symbol "(" ?
This VCD file is dump by VCS, with zero delay instruction shown below.
vcs -v -R -debug_all -sverilog -full64 +delay_mode_zero +nospecify +notimingcheck $library_path $verilog_file_path $testbench_file_path
And here is my testbench:
This VCD file is dump by VCS, with zero delay instruction shown below.
vcs -v -R -debug_all -sverilog -full64 +delay_mode_zero +nospecify +notimingcheck $library_path $verilog_file_path $testbench_file_path
And here is my testbench:
Code:
timescale 1ns / 1ps
`delay_mode_zero
module c17_tb;
reg N1,N2,N3,N6,N7;
wire N22,N23;
c17 uut(.N1(N1), .N2(N2), .N3(N3), .N6(N6), .N7(N7), .N22(N22), .N23(N23));
initial begin
$dumpfile("./c17_waveform.vcd");
$dumpvars(0, c17_tb);
N1 = 0;
N2 = 0;
N3 = 0;
N6 = 0;
N7 = 0;
repeat (100000) begin
#1;
N1 = $random % 2;
N2 = $random % 2;
N3 = $random % 2;
N6 = $random % 2;
N7 = $random % 2;
end
#10;
$finish;
end
endmodule
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