neocool
Member level 4
multiple clocks ise
I have created a test bench using Xilinx ISE software with multiple clocks and realized that I need to change dependency of a signal on different clock. 1. How would you do it without starting from scratch (tb wizzard)?
2. When creating a testbench with multiple clocks, ISE asks to enter dependency of signals on the relevant clocks. What is the purpose it? Isn't it enough just to use one system clock? I assume everything else needed for simulation should have been already specified in your tested VHDL code.
For example, if your clock is 40MHz, and bit clock is just 20MHz. There're clk, data_in, data_out, trigger_out, bit_clk_in, bit_clk_out. Which signals should you make dependent on which clock (clk and bit_clk_in) assuming that data_out and bit_clk_out are delayed by several clocks (variable depending on type of data_in)?
Regards
I have created a test bench using Xilinx ISE software with multiple clocks and realized that I need to change dependency of a signal on different clock. 1. How would you do it without starting from scratch (tb wizzard)?
2. When creating a testbench with multiple clocks, ISE asks to enter dependency of signals on the relevant clocks. What is the purpose it? Isn't it enough just to use one system clock? I assume everything else needed for simulation should have been already specified in your tested VHDL code.
For example, if your clock is 40MHz, and bit clock is just 20MHz. There're clk, data_in, data_out, trigger_out, bit_clk_in, bit_clk_out. Which signals should you make dependent on which clock (clk and bit_clk_in) assuming that data_out and bit_clk_out are delayed by several clocks (variable depending on type of data_in)?
Regards