Multiple clock domain sync

[vintujose]

Hi I am a new bee
I need to how is the sync between two clock domains is done .
How can i design it using VHDL without using the Async FIFO .

if anybody has a generic code please pass on to me
with regards
kewl

 

[Iouri]

PLease use search in this forum, that topic had been addressed few times

 

[shnain]

Hi,

Maybe you already got the answer, but anyway :

To sync a signal coming from another clock domain you can use a double FF synchronizer, for example :

process(clk, rst)
begin

  if rst = '0' then
    in_sig = '0';

  elsif rising_edge(clk) then
    tmp <= in_sig;
    in_sig_s <= tmp;
  end if;

end process;

where in_sig is the input signal to be synchronized and in_sig_s is the signal synchronized to clock domain clk

hope it helps !
yours,
Said

 

[xtcx]

Hi shnain, your solution is ok, but my case is a bit different,can you solve it?....Like my design(FPGA) communicates with a CODEC which has a clk of 2MHz,but however the codec is a master here...You can't make any handshaking to that.Because it's clk is not controllable.....Is there any solution to sync this clk?....and sample the data with my synchronized FPGA clk?...

 

[robinh]

Clock domain synchronization is not a simple solution, because of the metastability problems. This problem is quite large and you should investigate a little on Internet to understand what it is. However, there is two solutions :

1 - for a single signal use 2 cascaded flip-flops, synchronized with the destination clock.

2 - for a dataflow, use a FIFO with two clock domains (the FIFO integrates the necessary logic to manage properly the clock domain crossing problems).

Good luck

 

[xtcx]

2 - for a dataflow, use a FIFO with two clock domains (the FIFO integrates the necessary logic to manage properly the clock domain crossing problems).

Do you mean, implementing Asynchronous FIFO?....