delay
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vhdl multiple architectures
Hi,
If I have designed several architectures i.e., (same function with multiple styles) within an entity, how does the Xilinx ISE 6 pick the architecture
in the design file? The documentation says it should pick the last one compiled. However, how do I know which one it compiled last?
Further, if I use "configuration" statement in VHDL to have the tool force pick the architecture I want, it still selects the one it wants. I understand many synthesizers do not support configurations. But XST does.
Delay (delayed by technology)
Hi,
If I have designed several architectures i.e., (same function with multiple styles) within an entity, how does the Xilinx ISE 6 pick the architecture
in the design file? The documentation says it should pick the last one compiled. However, how do I know which one it compiled last?
Further, if I use "configuration" statement in VHDL to have the tool force pick the architecture I want, it still selects the one it wants. I understand many synthesizers do not support configurations. But XST does.
Delay (delayed by technology)
