multiphase clocking with DC

[kis1]

Is it possible to do multiphase clocking with synopsys DC? I had an application in which i want to specify a group of flipflops to which i want to give clk1, another group of flipflops to which clk2, another to which clk3...is it possible to this with DC or any sysnopsys tool? How?

 

[sandusty]

Have you tried it? It should be straight forward.

 

[realtek]

If you don't want DC process your muticlock (without buffer....)
try
set_dont_touch_network "your clock"
DC will ignore calculate the clock loading ..., then it shoule be the same as what you design.